Photolithography Process Development Engineer (Advanced Patterning)

Texas Instruments; Lehi (UT); On-site; USD 90,000 - 120,000; Full time

Job summary

Texas Instruments in Lehi, Utah, is seeking a skilled Process Development Engineer to focus on advanced-node semiconductor manufacturing, specifically in photolithography and litho-etch integration. The ideal candidate will possess deep expertise in semiconductor processes, work directly with simulation software, and collaborate with cross-functional teams to optimize manufacturing techniques. This role includes responsibilities for improving Critical Dimension Uniformity and implementing resolution enhancement techniques. Come help shape innovation at Texas Instruments!

Qualifications

• Experience in semiconductor manufacturing processes, particularly in photolithography.
• Strong analytical skills with a focus on optimizing patterning results.
• Ability to collaborate with cross-functional teams.

Responsibilities

• Utilize lithography simulation software to analyze and optimize processes.
• Identify defects and improve Critical Dimension Uniformity using advanced metrology.
• Work with vendors to evaluate and improve materials and tools.
• Analyze process data and implement robust improvements.
• Define and lead pathfinding activities for new patterning technology.

Skills

Lithography simulation software

Advanced metrology techniques

Data analysis

Statistical Process Control (SPC)

Design of Experiments (DOE)

Education

Bachelor's or Master's degree in Engineering or related field

Tools

CD-SEM

Prolith

S-Litho

Job description

Change the world. Love your job.

We’re at the forefront of an exciting era of semiconductor innovation at Texas Instruments’ LFAB in Lehi, Utah — home to our state-of-the‑art 300mm manufacturing facility now ramping our most advanced 28nm analog and embedded process technology in the heart of the Silicon Slopes. As part of our Advanced Technology Development (ATD) organization, you will be challenged with developing and characterizing the next generation node. We are seeking a highly skilled and hands‑on Process Development Engineer with deep expertise in advanced‑node semiconductor manufacturing. This role focuses on the next generation 20nm‑class logic technologies, with primary responsibility for photolithography and litho‑etch integration, including advanced patterning techniques such as pitch doubling (SADP/LELE). This role will also work directly with the Resolution Enhancement Techniques (RET) team to create Optical Proximity Corrections (OPC) and validate final pattern meets design tolerance.

You will play a critical role in developing, optimizing, and scaling patterning processes to meet aggressive performance, yield, and manufacturability targets. This is a high‑impact position working at the intersection of lithography, materials science, and plasma etch.

Responsibilities

• Modeling & Simulation:Utilize lithography simulation software (e.g., Prolith, S‑Litho) to analyze process windows and optimize patterning results.
• Metrology & Yield Improvement:Utilize advanced metrology (CD‑SEM, Overlay, Scatterometry) to identify defects and improve Critical Dimension Uniformity (CDU) and overlay performance.
• Vendor & Subsystem Interaction:Work with equipment vendors to evaluate new materials, photoresists, and tool hardware upgrades.
• Data Analysis & SPC:Analyze process data, identify root cause, and implement robust process improvements. Apply Statistical Process Control (SPC) and Design of Experiments (DOE) to develop new processes to enable Litho shrink processes.
• Pathfinding & Technology Transfer:Define pathfinding activities for new patterning technology, evaluating High NA Immersion for next‑generation nodes. Lead technology transfer from R&D to HVM for photolithography processes.
  • Drivelitho-etch integration (LE, LELE, SADP / pitch doubling)for advanced patterning schemes.
  • Develop and implementresolution enhancement techniques (RET) andoptical proximity correction (OPC)strategies.
  • Evaluate and selectmaterials systems, including photoresists, hard masks, and anti-reflective coatings.
  • Characterize and reduce patterning defects, includingline edge roughness (LER), CD variation, and overlay errors.
  • Collaborate closely with Etch team to optimizepattern transfer, profile control, and CD uniformityInterface with cross-functional teams including design, integration, yield, and manufacturing.