Overlay Development Engineer – Lithography

Intel

Hillsboro (OR)

Hybrid

USD 156,000 - 255,000

Full time

10 days ago

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Benefits offered by this job

Stock bonuses
Competitive compensation
Excellent health plans

Job summary

Intel is seeking a senior LTD Module Development Engineer in Hillsboro, OR, to drive scientific research for next-generation device architectures. You will design and analyze experiments to meet stringent process specs and contribute to IP development.

Applicants should bring 12+ years (BS), 10+ (MS), or 7+ (PhD) in related STEM fields, with hands-on lithography and overlay experience, including DOE/SPC practices, and familiarity with ASML equipment.

Qualifications

  • Education: Bachelor's with 12+ years, Master's with 10+ years, or Ph.D. with 7+ years in Materials Science, Chemical Engineering, Chemistry, Physics, Mechanical Eng, Electrical Eng, or related STEM.
  • 7+ years hands-on lithography industry experience.
  • Experience with advanced node overlay development processes.
  • Proven ability to troubleshoot process impacts on overlay mark performance.
  • Experience with integrated process development to co-optimize process flows and overlay mark design.
  • DOE, SPC, and data analysis proficiency.

Responsibilities

  • Lead scientific research enabling the manufacture of innovative device architectures and related realizations.
  • Design, execute, and analyze experiments to meet engineering specifications for their process.
  • Participate in development of intellectual property.
  • Integrate steps necessary for the manufacture of complex microprocessors.
  • Ramp to manufacturing volumes and transfer technology to manufacturing via Copy Exactly Methodology.

Skills

Strong communication
Cross-functional collaboration
DOE
SPC
Data analysis
Troubleshooting

Education

Bachelor's degree in Materials Science or related STEM
Master's degree in related field
Ph.D. in related field

Tools

ASML EUV/DUV scanners

Job description

Intel is seeking a senior LTD Module Development Engineer in Hillsboro, OR, to drive scientific research for next-generation device architectures. You will design and analyze experiments to meet stringent process specs and contribute to IP development.

Applicants should bring 12+ years (BS), 10+ (MS), or 7+ (PhD) in related STEM fields, with hands-on lithography and overlay experience, including DOE/SPC practices, and familiarity with ASML equipment.

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