Remote: Mid Core Design Verification for RISC-V CPUs

Tenstorrent; St. Louis (MO); Remote; USD 100,000 - 500,000; Full time

Job summary

Tenstorrent is seeking a Mid Core Design Verification Engineer to verify the next generation of high-performance RISC-V CPU cores. You will develop verification strategies, build robust test environments, and drive issues to closure, working closely with CPU architects and RTL designers.

The role is remote, based out of North America or Spain, with offers aligned to experience level. You will contribute to verification of complex pipelines, caches, and out-of-order execution while advancing AI/

Qualifications

• 6+ years of experience in design verification for CPUs, SoCs, ASICs, or similar complex digital designs.
• Strong experience with SystemVerilog and UVM, including testbench development, constrained-random testing, assertions, and functional coverage.
• Understanding of CPU architecture/microarchitecture concepts such as pipelines, out-of-order execution, caches, and scheduling.
• Experience debugging RTL and simulation failures using waveforms and common tools.
• Proficiency in C/C++ or Python and collaboration with RTL designers and architects.

Responsibilities

• Verify high-performance RISC-V CPU cores with robust test environments and test benches.
• Develop verification strategies, uncover corner cases, and drive issues to closure.
• Collaborate with CPU architects and RTL engineers across the full design lifecycle.

Skills

SystemVerilog

UVM

Testbench development

C/C++ or Python

Debug RTL

Job description

Tenstorrent is seeking a Mid Core Design Verification Engineer to verify the next generation of high-performance RISC-V CPU cores. You will develop verification strategies, build robust test environments, and drive issues to closure, working closely with CPU architects and RTL designers.

The role is remote, based out of North America or Spain, with offers aligned to experience level. You will contribute to verification of complex pipelines, caches, and out-of-order execution while advancing AI/