NAND Memory Design Engineer – AI-Driven Innovation

Micron Technology, Inc.; San Jose (CA); On-site; USD 83,000 - 198,000; Full time

Job summary

Micron Technology, Inc. in California is seeking a Design Engineer to assist with the design, layout, and optimization of datapath circuits for NAND flash memory. You will collaborate with engineers on technical datapath projects and contribute to design planning, layout, and validation.

The role emphasizes high-speed IO, power and area optimization, and the use of AI to accelerate workflows and research within the Non-Volatile Engineering Group.

Qualifications

• BS or MS in Electrical Engineering with 0–2 years of full-time semiconductor experience.
• Understanding of physical design flows, high-speed IO performance, power/area optimization, and chip architecture/floorplanning.
• Ability to actively participate in complex design projects and communicate progress clearly.

Responsibilities

• Manage major IO/datapath block (e.g. input receiver, serializer, deserializer, clock distribution, equalizer, ZQ calibration, ONFI training features, wave pipeline) to meet specifications and verify functionality and performance
• Model parasitics and review layout regularly and find opportunities of improving area/power
• Communicate with project integration and other functional teams on specifications of major block interfaces
• Communicate with PE to drive silicon experiments and propose and implement fixes for yield improvement and silicon debugging
• Document and review final results with senior engineers and project partners
• Leverage AI and automation to facilitate workflow acceleration and ongoing research

Skills

AI for design

CMOS/BSIM understanding

Education

BS or MS in Electrical Engineering

PhD in Electrical Engineering

Job description

Micron Technology, Inc. in California is seeking a Design Engineer to assist with the design, layout, and optimization of datapath circuits for NAND flash memory. You will collaborate with engineers on technical datapath projects and contribute to design planning, layout, and validation.

The role emphasizes high-speed IO, power and area optimization, and the use of AI to accelerate workflows and research within the Non-Volatile Engineering Group.