Memory Design Engineer — AI-Enabled Datapath Specialist

Micron Technology, Inc; San Jose (CA); On-site; USD 100,000 - 130,000; Full time

Job summary

Micron Technology, Inc. in San Jose is seeking a new college graduate Design Engineer for the NVEG group.

You will contribute to datapath design, layout, and optimization for NAND flash memory, making architectural choices and collaborating across engineering teams to meet project deadlines. Minimum qualifications include a BS/MS in Electrical Engineering with 0–2 years of experience and a strong understanding of physical design flows, high‑speed IO performance, and chip architecture.

Qualifications

• Understanding of physical design flows, high‑speed IO circuit performance, power and area optimization, and chip architecture/floorplan.
• Coursework or experience related to CMOS design and silicon layout.
• Ability to collaborate across multi-disciplinary teams on complex projects.

Responsibilities

• Manage major IO/datapath blocks to meet specifications and verify functionality.
• Model parasitics and review layout for area/power improvements.
• Communicate with project teams on block interface specs.
• Collaborate with Process Engineering to drive silicon experiments and fixes.
• Document results and present findings to engineers and partners.
• Leverage AI and automation tools to accelerate design workflows.

Skills

Physical design flows

High-speed IO performance

Power and area optimization

Chip architecture/floorplan

Education

BS in Electrical Engineering

MS in Electrical Engineering

Job description

Micron Technology, Inc. in San Jose is seeking a new college graduate Design Engineer for the NVEG group.

You will contribute to datapath design, layout, and optimization for NAND flash memory, making architectural choices and collaborating across engineering teams to meet project deadlines. Minimum qualifications include a BS/MS in Electrical Engineering with 0–2 years of experience and a strong understanding of physical design flows, high‑speed IO performance, and chip architecture.