Senior NAND Design Engineer — Advanced Memory Architect

Micron Technology; San Jose (CA); On-site; USD 116,000 - 246,000; Full time

Job summary

Micron Technology is seeking a Senior Engineer in the NVE Design Engineering Core to advance best-in-class memory products and mixed-signal circuit design. You will contribute to core development and participate in full-chip integration, impacting performance and power across NAND architectures.

You will collaborate with Firmware, Analog, and Design Validation teams, develop waveforms, run simulations, and drive layout integration with AI-assisted design tools to accelerate tasks.

Qualifications

• Ph.D. preferred; MS in Electrical Engineering required; 4+ years NAND design experience.
• Strong fundamentals in semiconductor and device physics; analog/mixed-signal design.
• Experience with NAND read/program/erase algorithms and CIM projects.
• Proficient in Python; Bash/Tcl a bonus; experience with CSV/JSON/SQLite.
• Knowledge of Cadence LVS/DRC and Verilog simulations.

Responsibilities

• Develop array waveforms with timing and biasing for NAND flash.
• Collaborate with Firmware, Analog, and Design Validation teams during implementation.
• Plan wordline/bitline path architectures per area, performance and power specs.
• Analyze die size costs and NAND power consumption; work with teams to optimize.
• Create and integrate Core and full-chip schematics; run SPICE simulations.
• Develop Python automation and AI-assisted tools for EDA tasks.
• Review and generate user documentation.

Skills

Python

Bash/Tcl

NAND design

Circuit debugging

Circuit verification

Layout planning

Scripting (CSV/JSON/SQLite)

Linux/UNIX

HSPICE/Verilog

Cadence LVS/DRC

Semiconductor physics

Education

MS in Electrical Engineering

Ph.D. preferred

Tools

Cadence design tools

LVS/DRC tools

Verilog

SPICE simulators

Job description

Micron Technology is seeking a Senior Engineer in the NVE Design Engineering Core to advance best-in-class memory products and mixed-signal circuit design. You will contribute to core development and participate in full-chip integration, impacting performance and power across NAND architectures.

You will collaborate with Firmware, Analog, and Design Validation teams, develop waveforms, run simulations, and drive layout integration with AI-assisted design tools to accelerate tasks.