NAND Design Engineer: IO & Datapath Architect

Micron Technology; San Jose (CA); On-site; USD 83,000 - 198,000; Full time

Benefits offered by this job

Medical, dental, and vision plans

Equity

Paid time off

Job summary

Micron Technology is seeking a Design Engineer to design, lay out, and optimize datapath circuits for NAND flash memory. You will make strategic architectural decisions, assess proposals, and collaborate with design, layout, and validation teams to meet timing and power targets.

The role requires a BS or MS in Electrical Engineering with 0–2 years of experience, understanding of physical design flows, high-speed IO performance, and a collaborative mindset.

Qualifications

• BS or MS in Electrical Engineering with 0–2 years of related experience.
• Understanding of physical design flows and high-speed IO performance.
• Ability to communicate progress and findings in cross-functional teams.

Responsibilities

• Design, layout, and optimize datapath circuits for NAND flash memory.
• Model parasitics and review layout to improve area and power.
• Define interfaces with project integration and other teams.
• Collaborate with Process Engineering for silicon experiments and yield fixes.
• Document final results with senior engineers and project partners.
• Leverage AI and automation to accelerate workflow.

Skills

Physical design basics

High-speed IO performance

Power and area optimization

Chip architecture/floorplanning

Effective communication

Education

BS/MS in Electrical Engineering

Tools

AI for design optimization

Job description

Micron Technology is seeking a Design Engineer to design, lay out, and optimize datapath circuits for NAND flash memory. You will make strategic architectural decisions, assess proposals, and collaborate with design, layout, and validation teams to meet timing and power targets.

The role requires a BS or MS in Electrical Engineering with 0–2 years of experience, understanding of physical design flows, high-speed IO performance, and a collaborative mindset.