ML-Driven Verification Engineer: RTL/UVM/SVA

VerifAI; San Francisco (CA); On-site; USD 120,000 - 180,000; Full time

Job summary

VerifAI in San Francisco designs verification engines that fuse RTL, ML, and AI to accelerate chip design cycles. You will contribute to developing AI-powered verification engines and work with customers to deploy scalable verification solutions.

The role emphasizes strong SystemVerilog/UVM skills, Python tooling, and experience with industry protocols, enabling rapid automation across design and verification teams.

Qualifications

• BS/MS EE/CS required or equivalent experience.
• Expertise in RTL design and verification.
• Strong knowledge of ML techniques applied to verification.
• Proficiency in SystemVerilog, UVM, and Python.

Responsibilities

• Design, develop, and accelerate VerifAI's AI Engines for chip design and verification.
• Collaborate with customers to deploy VerifAI solutions.

Skills

ML Algorithms

SystemVerilog

UVM

Python

Logic Simulation

Education

BS/MS EE/CS

Tools

AXI

PCIe

RISC-V

ARM

Job description

VerifAI in San Francisco designs verification engines that fuse RTL, ML, and AI to accelerate chip design cycles. You will contribute to developing AI-powered verification engines and work with customers to deploy scalable verification solutions.

The role emphasizes strong SystemVerilog/UVM skills, Python tooling, and experience with industry protocols, enabling rapid automation across design and verification teams.