Mixed-Signal Verification Engineer – Power Management ICs

TYLsemi; United States; Remote; USD 140,000 - 210,000; Full time

Job summary

TYLsemi is seeking a Senior Mixed-Signal Verification Engineer to develop and execute verification plans for high-current IVR designs. You will build analog behavioral models and perform analog-digital co-simulation using Cadence/Xcelium, Spectre, VCS, or AMS Designer.

You will verify digital control loops, create testbenches for key metrics, run regressions across PVT corners, and debug issues at transistor and behavioral levels.

Qualifications

• 5+ years of hands-on mixed-signal verification in PMICs or analog/mixed-signal SoCs.
• Proficiency in mixed-signal simulation flows and RNM/Verilog-A modeling.
• Experience with AMS co-simulation (AMS, VCS+Spectre, Xcelium).
• Solid knowledge of power converter topologies (buck, multi-phase, 3-level).
• Understanding digital control concepts for power converters (PID, DPWM).
• MATLAB/Simulink for system-level modeling.
• SystemVerilog/UVM for digital/mixed-signal testbenches.
• Familiarity with Cadence Virtuoso/Spectre or Synopsys CustomSim.
• Understanding analog non-idealities (quantization, loop delay, PDN resonances).
• BSEE / MSEE with 8+ years of experience.

Responsibilities

• Develop and execute mixed-signal verification plans for high-current IVR designs.
• Build and maintain analog behavioral models (Verilog-A / SystemVerilog real-number modeling).
• Perform analog-digital co-simulation using Cadence/Xcelium, Spectre, VCS, or AMS Designer.
• Verify digital control loops.
• Create testbenches for metrics like transient response, loop stability, efficiency, ripple, protections, startups.
• Run regressions across PVT corners and Monte-Carlo analyses.
• Debug mixed-signal issues at transistor and behavioral levels.
• Collaborate with analog and digital designers to close verification coverage.
• Develop automated verification scripts and improve methodology.
• Support post-silicon validation by correlating with lab measurements.

Skills

Mixed-signal verification

RNM Verilog-A

AMS co-simulation

Digital control concepts

SystemVerilog/UVM

Power converter knowledge

Matlab/Simulink

Python scripting

Education

BSEE / MSEE

Tools

Cadence Virtuoso

Spectre

Xcelium

Synopsys CustomSim

Job description

WhatYou’llDo

• Develop and execute mixed-signal verification plans for high-current IVR designs.
• Build andmaintainanalog behavioral models (Verilog-A /SystemVerilogreal-number modeling) for power stages, integrated inductors, PDN, and analog blocks.
• Perform analog-digital co-simulation using industry-standard tools (CadenceXcelium+Spectre, Synopsys VCS +FineSim/CustomSim, or AMS Designer).
• Verify digital control loops
• Create testbenches for key performance metrics: transient response (load steps), loop stability, efficiency, ripple, over-current / over-voltage protection, and startup/shutdown sequences.
• Run regressions across PVT corners, Monte-Carlo analysis, and corner-case scenarios.
• Debug mixed-signal issues at both transistor-level and behaviorallevel.
• Collaborate closely with analog designers, digital designers, and system engineers to close verification coverage.
• Develop automated verification scripts and improve verificationmethodologyfor faster turnaround.
• Support post-silicon validation by correlating simulation results with lab measurements.

WhatWe’reLooking For

• 5+ years of hands-on experience in mixed-signal verification of power management ICs or analog/mixed-signal SoCs.
• Strongproficiencyin mixed-signal simulation flows :
• Real Number Modeling (RNM) and Verilog-A behavioral modeling
• Analog-digital co-simulation (AMS, VCS +Spectre,Xcelium)
• Solid understanding of power converter topologies (buck, multi-phase, 3-level buck, switched-capacitor converters).
• Good knowledge of digital control concepts for power converters (PID controllers, DPWM, digital feedback loops).
• Experience with MATLAB/Simulink for system-level modeling and testbench reference generation.
• ProficiencyinSystemVerilogand UVM for digital/mixed-signaltestbenches.
• Familiarity with Cadence Virtuoso,Spectre, or SynopsysCustomSimfor analog simulation.
• Understanding of analog non-idealities (quantization effects, loop delay, sensor offsets, PDN resonances, inductor non-linearities).
• BSEE / MSEE with8+yearsrelevant experience.

Nice to Have

• Experience verifying high-frequency IVRs,PoLregulators, or high-current power delivery systems.
• Experience with SIMPLIS, PLECS, or Simulink for system-level power electronics validation.
• Familiarity with digital PID controller verification and fixed-point arithmetic effects.
• Exposure toadvanced packaging and on-die inductor modeling.
• Scripting skills in Python, Perl, orTclfor automation.