Sr Principal Mixed Signal Verification Engineer

Qorvo, Inc.; Richardson (TX); On-site; USD 130,000 - 160,000; Full time

Job summary

Qorvo, Inc. in Richardson, TX, is looking for a Sr Principal Mixed Signal Verification Engineer. This role focuses on developing and executing design verification plans for power-management ICs, with responsibilities including test development within UVM environments. Applicants should possess a Bachelor's degree and have 15+ years of industry experience.

The ideal candidate will demonstrate expertise in mixed-signal circuit design and verification, and must be proficient in UVM and related methodologies. Position may require limited travel and offers a collaborative work environment.

Qualifications

• 15+ years of experience or equivalent education in AMS design or verification.
• Proficiency in UVM environments including test cases and coverage models.
• In-depth knowledge of power-management components.

Responsibilities

• Serve as customer-facing for power-management ICs.
• Develop and execute metric-driven design verification plans.
• Collaborate with design team to resolve verification issues.

Skills

Mixed-signal circuit design and verification

UVM environments

Problem-solving skills

Communication skills

Education

Bachelor’s degree in electrical engineering or related field

Master’s degree in electrical engineering or related field

Tools

Spice/Spectre

Python scripting

Job description

Sr Principal Mixed Signal Verification Engineer

Experience Level: Professional

Job Type: Regular

Location: Richardson, TX 75081

Requisition ID: 10289

Responsibilities

• Serve as customer-facing for catalog and custom power-management ICs including motor driver, power-loss protection, point of load, and battery management IC solutions.
• Develop and execute metric-driven design verification plans based upon IC functional, performance, and test specifications, with a strong focus on the customer use-case.
• Develop constrained random tests and automated checkers within our TLDV UVM environment.
• Build high-performance, accurate RNM or VerilogAMS models to support TL simulation.
• Collaborate with design team to resolve issues identified during verification.
• Partner with internal design and test teams to ensure device first-pass testability.
• Continuously improve and align verification methodologies with industry best practices.
• Automate verification tasks where applicable.

Required Qualifications

• Bachelor’s degree in electrical engineering or a related field, with strong focus on mixed-signal circuit design and verification.
• 15+ years of experience or an equivalent amount of advanced education and experience in AMS design or verification of analog and power-management ICs.
• Proficiency in UVM environments, including test cases, coverage models, and global checkers.
• In-depth knowledge of power-management building blocks such as LDO, amplifiers, bandgaps, DCDC regulators, oscillators, and asynchronous state machines.
• Excellent problem‑solving and debugging skills.
• Effective communication and collaboration skills.
• Expertise in mixed-signal concepts such as Spice/Spectre and event-based simulator, co-simulation environment, simulation debug, silicon debug.

Preferred Qualifications

• Master’s degree in electrical engineering or a related field, with strong focus on mixed-signal circuit design and verification.
• Experience in Top-Down Design Methodology.
• Proficiency in shell or Python scripting.
• Familiarity with SV-UDN/EENET modeling techniques.
• Experience with both GUI and command-line simulation flows.
• Proficiency with SV Assertions and Functional coverage.
• Understanding integration of AI into a verification workflow.

Other

• 10% or less domestic or international travel may be required.

We are an Equal Employment Opportunity (EEO) employer and welcome all qualified applicants. Applicants will receive fair and impartial consideration without regard to any characteristics protected by applicable law, including race, color, religion, sex (as defined by law), national origin, age, military or veteran status, genetic information, or disability.