Senior Mixed-Signal Verification Engineer – Power ICs

TYLsemi; United States; Remote; USD 140,000 - 210,000; Full time

Job summary

TYLsemi is seeking a Senior Mixed-Signal Verification Engineer to develop and execute verification plans for high-current IVR designs. You will build analog behavioral models and perform analog-digital co-simulation using Cadence/Xcelium, Spectre, VCS, or AMS Designer.

You will verify digital control loops, create testbenches for key metrics, run regressions across PVT corners, and debug issues at transistor and behavioral levels.

Qualifications

• 5+ years of hands-on mixed-signal verification in PMICs or analog/mixed-signal SoCs.
• Proficiency in mixed-signal simulation flows and RNM/Verilog-A modeling.
• Experience with AMS co-simulation (AMS, VCS+Spectre, Xcelium).
• Solid knowledge of power converter topologies (buck, multi-phase, 3-level).
• Understanding digital control concepts for power converters (PID, DPWM).
• MATLAB/Simulink for system-level modeling.
• SystemVerilog/UVM for digital/mixed-signal testbenches.
• Familiarity with Cadence Virtuoso/Spectre or Synopsys CustomSim.
• Understanding analog non-idealities (quantization, loop delay, PDN resonances).
• BSEE / MSEE with 8+ years of experience.

Responsibilities

• Develop and execute mixed-signal verification plans for high-current IVR designs.
• Build and maintain analog behavioral models (Verilog-A / SystemVerilog real-number modeling).
• Perform analog-digital co-simulation using Cadence/Xcelium, Spectre, VCS, or AMS Designer.
• Verify digital control loops.
• Create testbenches for metrics like transient response, loop stability, efficiency, ripple, protections, startups.
• Run regressions across PVT corners and Monte-Carlo analyses.
• Debug mixed-signal issues at transistor and behavioral levels.
• Collaborate with analog and digital designers to close verification coverage.
• Develop automated verification scripts and improve methodology.
• Support post-silicon validation by correlating with lab measurements.

Skills

Mixed-signal verification

RNM Verilog-A

AMS co-simulation

Digital control concepts

SystemVerilog/UVM

Power converter knowledge

Matlab/Simulink

Python scripting

Education

BSEE / MSEE

Tools

Cadence Virtuoso

Spectre

Xcelium

Synopsys CustomSim

Job description

TYLsemi is seeking a Senior Mixed-Signal Verification Engineer to develop and execute verification plans for high-current IVR designs. You will build analog behavioral models and perform analog-digital co-simulation using Cadence/Xcelium, Spectre, VCS, or AMS Designer.

You will verify digital control loops, create testbenches for key metrics, run regressions across PVT corners, and debug issues at transistor and behavioral levels.