Layout Engineer

eTeam; Austin (TX); On-site; USD 120,000 - 190,000; Full time

Job summary

eTeam seeks an experienced High-Speed Analog Layout Engineer to design physical silicon layouts for high-frequency mixed-signal blocks. You will handle floor planning, block integration, and co-design with packaging considerations.

Ideal candidates have 5–12+ years in deep sub-micron CMOS/FinFET nodes, with critical experience at N3 and N5 nodes, and a track record addressing LOD, WPE, LDE and robust noise control.

Qualifications

• 5–12+ years of hands-on custom IC layout experience in deep sub-micron CMOS/FinFET nodes
• Experience at lower nodes (N3, N5) is critical for this position
• Proven ability to address layout-dependent effects (LOD, WPE, LDE) and noise

Responsibilities

• Design physical silicon layout for high-speed mixed-signal circuits (SerDes, ADCs, DACs, PLLs)
• Perform floor planning and integration of block-level and chip-top-level layouts
• Address parasitic effects, device matching, guard rings and isolation/shielding
• Ensure design-rule checks (DRC), layout-versus-schematic (LVS), ERC and ESD protection

Skills

Analog layout

High-speed design

Floor planning

Parasitic & noise control

Job description

• High-Speed Analog Layout Engineer designs the physical silicon layout for high-frequency or high-speed mixed-signal circuits (such as SerDes, ADCs, DACs, PLLs, and High speed blocks).
• Floor Planning & Integration: Create block-level and chip-top-level floor plans, manage hierarchical block integration, and handle micro-bump or package-aware co-design
• Parasitic & Noise Control: Address layout-dependent effects (LOD, WPE, LDE), device matching, common-centroid structures, guard rings, and isolation or shielding (coaxial, differential, ground shields). [1, 2, 3]
• Reliability & Verification: Ensure complete closure on DRC (Design Rule Check), LVS (Layout Versus Schematic), ERC, antenna rules, EM/IR (Electromigration / Infrared drop) reliability, and ESD protection
• Generally 5 to 12+ years of hands-on custom IC layout experience in deep sub-micron or advanced CMOS/FinFET nodes (such as TSClient N3, N5, N7)
• Experience at Lower node (N3, N5) is critical for this position.