Our client is seeking an experienced Analog/Mixed-Signal Layout Engineer to join an advanced custom IC layout team.
This is a hands‑on individual contributor position focused on the development of high‑quality custom layouts for complex analog and mixed‑signal circuitry in advanced FinFET technologies. The successful candidate will work closely with circuit designers throughout the layout process, applying strong technical judgment to address matching, parasitics, noise coupling, supply integrity, and other performance‑critical layout considerations.
The role offers exposure to a broad range of analog and mixed‑signal IP, including high‑speed and high‑frequency circuits operating at GSPS and GHz‑class performance levels.
Key Responsibilities
- Develop high-quality block‑level custom layouts for advanced analog and mixed‑signal circuits.
- Work on a range of IP including ADCs, DACs, PLLs, bandgaps, LDOs, bias circuits, operational amplifiers, LNA/mixer circuitry, LO distribution, inductors, and digital macros.
- Work closely with circuit designers to understand design intent and resolve layout‑related technical challenges.
- Apply advanced layout techniques to optimize matching, parasitic performance, noise coupling, supply integrity, and signal performance.
- Implement custom layouts using Cadence Virtuoso.
- Perform LVS and DRC verification using Calibre.
- Generate and analyze parasitic extraction using StarRC, QRC, or similar tools.
- Identify and mitigate layout‑dependent effects in advanced FinFET technologies.
- Take ownership of assigned blocks and drive layout implementation through completion.
- Support integration activities and collaborate with engineering teams across multiple sites.
- Contribute to the continuous improvement of custom layout methodologies and best practices.
REQUIRED QUALIFICATIONS
- Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related field, with approximately 6+ years of relevant custom layout experience, or equivalent experience.
- Minimum 2 years of hands‑on block‑level FinFET custom analog, mixed‑signal, or RF layout experience at 7nm and below.
- Demonstrated high‑speed and high‑frequency layout experience involving GSPS‑class and/or GHz‑class circuitry.
- Strong experience with block‑level custom analog and mixed‑signal layout.
- Proficiency with Cadence Virtuoso.
- Experience with Calibre LVS and DRC.
- Experience with parasitic extraction using StarRC, QRC, or similar tools.
- Strong understanding of layout‑dependent effects and practical mitigation techniques.
- Solid understanding of analog and mixed‑signal circuit operation and associated layout considerations.
- Experience working closely with circuit designers to address parasitic, matching, coupling, and performance‑related layout challenges.
- Ability to work independently and take technical ownership of assigned layout blocks.
PREFERRED QUALIFICATIONS
- Experience with top‑level layout integration and floorplanning.
- Experience with Cadence Innovus.
- Exposure to standard‑cell place‑and‑route.
- Experience integrating digital macros with custom analog or mixed‑signal circuitry.
- Experience across both mixed‑signal and RF layout.
- Experience working with engineering teams across multiple sites.
- Experience analyzing parasitic extraction results to identify and resolve performance degradation.
- Experience with EM/IR analysis and implementing layout improvements based on analysis results.
- Experience with advanced process‑rule considerations, including multiple‑patterning processes.
DESIRED EXPERIENCE
Candidates with experience in one or more of the following areas are particularly relevant:
- High‑speed ADC layout.
- High‑speed DAC layout.
- SerDes or other high‑speed mixed‑signal circuitry.
- PLL and clocking circuitry.
- Analog front‑end circuitry.
- Power management and supporting analog blocks.
- Mixed‑signal circuits operating at GSPS or GHz‑class performance levels.
Experience spanning both analog/mixed‑signal and RF circuitry is advantageous. Strong mixed‑signal candidates without direct RF experience can also be well aligned.
Direct experience within a specific end market is not required, and candidates from adjacent high‑speed mixed‑signal backgrounds may be considered where the underlying technical experience is relevant.
INTERESTED
We are committed to submitting suitable candidates for this vacancy to our client ASAP. For more information, contact Jaimie Javier at PER Recruitment on LinkedIn.