Memory Validation Engineer — LPDDR5/6 & Automation

VisLab (an Ambarella Inc. company); Kentucky; On-site; USD 152,000 - 179,000; Full time

Job summary

VisLab, an Ambarella Inc. company, seeks an engineer for the memory subsystem (training and calibration) across LPDDR5/5X and LPDDR6. You will build the data-driven test infrastructure and analyze lab data to improve stability and performance.

You will collaborate with field teams, debug real customer issues, and influence next-generation memory controller designs. The role emphasizes automation, lab bring-up, and reliability under real-world conditions.

Qualifications

• 4+ years in memory validation, memory controller design, SoC validation, or a closely related area.
• Hands-on experience with LPDDR5/5X and LPDDR6, and familiarity with JEDEC specifications.
• Experience owning or contributing to memory training and calibration code, with C/firmware skills and Python for test automation.
• Practical debug skills on real hardware and data-driven analysis.

Responsibilities

• Own the memory training and calibration code for LPDDR5/5X and LPDDR6 across parts and boards.
• Collect and analyze memory subsystem data from lab testing, customer platforms, and internal validation.
• Build automation for memory stability testing, performance characterization, speed binning, and regression analysis.
• Debug real customer issues with field teams, driving problems to root cause and closure.
• Turn system behavior into insights that improve memory controller robustness and performance.
• Influence future silicon with data-backed architectural and design enhancements.
• Validate power-saving features across real-world use cases and support silicon bring-up.

Skills

Memory validation

Memory controller design

C firmware

Python automation

Data analysis

Debug techniques

Bench instrumentation

Customer collaboration

Tools

Logic analyzers

Protocol analyzers

Oscilloscope

Job description

VisLab, an Ambarella Inc. company, seeks an engineer for the memory subsystem (training and calibration) across LPDDR5/5X and LPDDR6. You will build the data-driven test infrastructure and analyze lab data to improve stability and performance.

You will collaborate with field teams, debug real customer issues, and influence next-generation memory controller designs. The role emphasizes automation, lab bring-up, and reliability under real-world conditions.