DDR Validation Lead — AI Accelerator & SoC Platforms

QUALCOMM, Inc.; San Diego (CA); On-site; USD 146,000 - 218,000; Full time

Benefits offered by this job

Annual bonus program

RSU grants

Benefits package

Job summary

Qualcomm Technologies, Inc. seeks an experienced DDR Validation Lead to drive end-to-end validation of LPDDR5X/LPDDR6 memory subsystems on AI Accelerator and flagship mobile platforms.

You will lead memory bring-up, performance validation, system stress, debugging, and production readiness from pre-silicon through post-silicon phases. In this role you will define validation strategies across emulation, FPGA, and silicon, partner with architectures, design and firmware teams, and mentor junior

Qualifications

• BS or MS or PhD in EE, CE, CS, or related field with 4+ years in ASIC design/validation.
• Strong knowledge of LPDDR4/5/5X/6 architectures and DDR controllers/PHYs.
• Experience with memory training, calibration algorithms and NoC architectures.
• Strong post-silicon debug experience.

Responsibilities

• Define and execute DDR validation strategy across emulation, FPGA, and silicon.
• Drive LPDDR5X/LPDDR6 bring‑up, training validation, frequency scaling, and low‑power state validation.
• Develop validation plans for memory functionality, performance, reliability, power and corner cases.
• Lead debug of DDR controller, PHY, firmware, SI/PI, timing, and system issues.
• Validate interactions between DDR, CPU, GPU, NPU, cache, NoC, and system software.
• Develop scalable automation, regression infrastructure, and debug analytics.
• Partner with Architecture, Design, Firmware, SI/PI, Package, and DRAM vendors to root‑cause issues.

Skills

C/C++

DDR validation

Memory subsystem validation

Post-silicon debugging

Low-level software development

System validation

Education

Bachelor's degree in EE/CE/CS or related

Master's degree in EE/CE/CS or related

PhD in EE/CS or related

Job description

Qualcomm Technologies, Inc. seeks an experienced DDR Validation Lead to drive end-to-end validation of LPDDR5X/LPDDR6 memory subsystems on AI Accelerator and flagship mobile platforms.

You will lead memory bring-up, performance validation, system stress, debugging, and production readiness from pre-silicon through post-silicon phases. In this role you will define validation strategies across emulation, FPGA, and silicon, partner with architectures, design and firmware teams, and mentor junior