Sr. Memory Validation Engineer

VisLab (an Ambarella Inc. company); Kentucky; On-site; USD 152,000 - 179,000; Full time

Job summary

VisLab, an Ambarella Inc. company, seeks an engineer for the memory subsystem (training and calibration) across LPDDR5/5X and LPDDR6. You will build the data-driven test infrastructure and analyze lab data to improve stability and performance.

You will collaborate with field teams, debug real customer issues, and influence next-generation memory controller designs. The role emphasizes automation, lab bring-up, and reliability under real-world conditions.

Qualifications

• 4+ years in memory validation, memory controller design, SoC validation, or a closely related area.
• Hands-on experience with LPDDR5/5X and LPDDR6, and familiarity with JEDEC specifications.
• Experience owning or contributing to memory training and calibration code, with C/firmware skills and Python for test automation.
• Practical debug skills on real hardware and data-driven analysis.

Responsibilities

• Own the memory training and calibration code for LPDDR5/5X and LPDDR6 across parts and boards.
• Collect and analyze memory subsystem data from lab testing, customer platforms, and internal validation.
• Build automation for memory stability testing, performance characterization, speed binning, and regression analysis.
• Debug real customer issues with field teams, driving problems to root cause and closure.
• Turn system behavior into insights that improve memory controller robustness and performance.
• Influence future silicon with data-backed architectural and design enhancements.
• Validate power-saving features across real-world use cases and support silicon bring-up.

Skills

Memory validation

Memory controller design

C firmware

Python automation

Data analysis

Debug techniques

Bench instrumentation

Customer collaboration

Tools

Logic analyzers

Protocol analyzers

Oscilloscope

Job description

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Job Description

About the role

Memory is where a lot of system-level problems come to die. Marginal timing, a corner-case power state transition, a customer platform that fails one boot in ten thousand — these issues are expensive to reproduce, slow to root-cause, and they tend to come back. We're hiring an engineer onto our ASIC design team to change that. You'll own the data and automation layer for our memory subsystem: building the test infrastructure that catches instability early, turning lab and field data into insight, and feeding what you learn back into the design of our next-generation memory controllers. This is a role for someone who likes both the oscilloscope and the dataframe. You'll spend time in the lab on silicon bring-up and just as much time writing the automation that means nobody has to do that debug by hand next time.

What You'll Do

• Own the memory training and calibration code. You'll develop, maintain, and tune the training and calibration routines that get LPDDR5/5X and LPDDR6 running reliably at speed across parts, boards, and operating conditions.
• Collect and analyze memory subsystem data from lab testing, customer platforms, and internal validation systems.
• Build automation for memory stability testing, performance characterization, speed binning, and regression analysis — expanding test coverage while cutting cycle time.
• Debug real customer issues alongside field teams and internal engineering groups, driving problems from first report to root cause to closure.
• Turn system behavior and failure analysis into insight that measurably improves memory controller robustness and performance.
• Influence future silicon. Propose architectural and design enhancements for next-generation memory controllers, backed by empirical data, customer feedback, and field experience.
• Validate power-saving features, characterizing them against performance, reliability, and power targets across a wide range of real-world use cases.
• Support silicon bring-up, qualification, and production readiness for memory subsystems.

What You'll Build

• Beyond closing individual issues, this role exists to create durable leverage:
• Stronger memory stability and reliability across the product line
• Dramatically shorter debug and validation cycles through automation
• Faster root-cause analysis and issue closure — which customers feel directly
• A lasting repository of memory characterization data and validation best practices
• Real-world insight that shapes future memory controller designs, so recurring issues stop recurring

Required

• 4+ years in memory validation, memory controller design, SoC validation, or a closely related area
• Hands-on experience with LPDDR5/5X and LPDDR6, and working familiarity with the relevant JEDEC specifications
• Experience owning or contributing to memory training and calibration code, with the C/firmware skills to maintain it Strong Python (or equivalent) for test automation and data analysis
• Practical debug skills on real hardware: bench instrumentation, protocol analyzers, logic analyzers, boot and stability failure triage
• Comfort with data at scale — you can take a pile of shmoo, margining, or regression results and find the signal in it
• Ability to work directly with customers and cross-functional teams under time pressure

Nice to have

• Silicon bring-up or post-silicon validation experience on a production program
• Signal integrity fundamentals: eye diagrams, jitter, and timing margin analysis on high-speed interfaces
• Experience with low‑power state validation (self‑refresh, power‑down, DVFS‑style transitions)
• Statistical analysis, ML, or dashboarding experience applied to hardware validation data
• Firmware or driver‑level exposure to the memory stack

Why this role

Running memory at state‑of‑the‑art speeds is genuinely hard, and it gets harder every generation. The margins shrink while the variables multiply: load, power, temperature, process spread. Silicon doesn't behave the way the simulations said it would, so the work becomes finding calibration and training approaches that hold up on real parts, in real systems, across the full operating envelope.

Then there's the second problem, which is doing all of that fast. A characterization flow that works in the lab is not a production flow. Getting from one to the other, reliably and on schedule, is its own engineering challenge.

And then there's DVFS, which is a beast in its own right. Validating frequency and voltage transitions without giving up stability or power targets means chasing failures that only appear at specific transition boundaries under specific conditions.

If that sounds like the kind of problem you want to spend your time on, this role has a steady supply of them. It also comes with real visibility: the data you produce goes to the architects planning the next generation, the field teams supporting customers today, and the validation teams qualifying silicon tomorrow. The decisions you influence show up in shipping products.

The base salary range is $152,000 - $179,000. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The successful candidate will have the opportunity to convert to a full‑time regular position. We also offer new‑hire RSU grants and the opportunity for annual RSU grants, as well as other highly competitive benefits.