Sr. Memory Validation Engineer

Ambarella Inc; Santa Clara (CA); Sur place; USD 152 000 - 179 000; Plein temps

Avantages offerts par ce poste

New-hire RSU grants

Competitive benefits

On-site 4 days a week

Résumé du poste

Ambarella Inc. is seeking an engineer for our memory subsystem on the ASIC design team. You will own the data and automation layer, building test infrastructure to catch instability early and turning lab and field data into design insights.

Responsibilities include training/calibration code for LPDDR5/5X and LPDDR6, data analysis from lab tests and customer platforms, and building automation for stability testing and regression analysis. On-site 4 days/week in Santa Clara.

Qualifications

• 4+ years in memory validation, memory controller design, SoC validation, or closely related area.
• Hands-on experience with LPDDR5/5X and LPDDR6; familiarity with JEDEC specs.
• Experience owning or contributing to memory training and calibration code; strong C/firmware skills and Python for test automation.
• Practical debug skills with bench instrumentation, protocol analyzers, and logic analyzers.
• Ability to work with data at scale and perform regression analysis to find signal in noise.
• Must work on-site 4 days a week in Santa Clara.

Responsabilités

• Own the memory training and calibration code for LPDDR5/5X and LPDDR6.
• Collect and analyze memory subsystem data from lab testing, customer platforms, and validation systems.
• Build automation for memory stability testing, performance characterization, speed binning, and regression analysis.
• Debug customer issues alongside field teams and internal engineering groups from report to root cause.
• Turn system behavior and failure analysis into actionable insights to improve memory controller robustness.
• Influence future silicon by proposing architectural and design enhancements backed by data and field experience.
• Validate power-saving features across real-world use cases; support silicon bring-up, qualification, and production readiness.

Connaissances

Memory validation

Calibration code ownership

Python

C/firmware

Data analysis

Bench instrumentation

Customer collaboration

Outils

JEDEC specifications

Description du poste

Memory is where a lot of system-level problems come to die. Marginal timing, a corner-case power state transition, a customer platform that fails one boot in ten thousand — these issues are expensive to reproduce, slow to root-cause, and they tend to come back.

We're hiring an engineer onto our ASIC design team to change that. You'll own the data and automation layer for our memory subsystem: building the test infrastructure that catches instability early, turning lab and field data into insight, and feeding what you learn back into the design of our next-generation memory controllers.

This is a role for someone who likes both the oscilloscope and the dataframe. You'll spend time in the lab on silicon bring-up and just as much time writing the automation that means nobody has to do that debug by hand next time.

What you'll do

• Own the memory training and calibration code. You'll develop, maintain, and tune the training and calibration routines that get LPDDR5/5X and LPDDR6 running reliably at speed across parts, boards, and operating conditions.
• Collect and analyze memory subsystem data from lab testing, customer platforms, and internal validation systems.
• Build automation for memory stability testing, performance characterization, speed binning, and regression analysis — expanding test coverage while cutting cycle time.
• Debug real customer issues alongside field teams and internal engineering groups, driving problems from first report to root cause to closure.
• Turn system behavior and failure analysis into insight that measurably improves memory controller robustness and performance.
• Influence future silicon. Propose architectural and design enhancements for next-generation memory controllers, backed by empirical data, customer feedback, and field experience.
• Validate power-saving features, characterizing them against performance, reliability, and power targets across a wide range of real-world use cases.
• Support silicon bring-up, qualification, and production readiness for memory subsystems.

What you'll build

• Beyond closing individual issues, this role exists to create durable leverage:
• Stronger memory stability and reliability across the product line
• Dramatically shorter debug and validation cycles through automation
• Faster root-cause analysis and issue closure — which customers feel directly
• A lasting repository of memory characterization data and validation best practices
• Real-world insight that shapes future memory controller designs, so recurring issues stop recurring

What we're looking for-

Required

• 4+ years in memory validation, memory controller design, SoC validation, or a closely related area
• Hands-on experience with LPDDR5/5X and LPDDR6, and working familiarity with the relevant JEDEC specifications
• Experience owning or contributing to memory training and calibration code, with the C/firmware skills to maintain it Strong Python (or equivalent) for test automation and data analysis
• Practical debug skills on real hardware: bench instrumentation, protocol analyzers, logic analyzers, boot and stability failure triage
• Comfort with data at scale — you can take a pile of shmoo, margining, or regression results and find the signal in it
• Ability to work directly with customers and cross-functional teams under time pressure
• Must work on-site 4 days a week in Santa Clara office.

Nice to have

1. Silicon bring-up or post-silicon validation experience on a production program

2. Signal integrity fundamentals: eye diagrams, jitter, and timing margin analysis on high-speed interfaces

3. Experience with low-power state validation (self-refresh, power-down, DVFS-style transitions)

4. Statistical analysis, ML, or dashboarding experience applied to hardware validation data

5. Firmware or driver-level exposure to the memory stack

Why this role

Running memory at state-of-the-art speeds is genuinely hard, and it gets harder every generation. The margins shrink while the variables multiply: load, power, temperature, process spread. Silicon doesn't behave the way the simulations said it would, so the work becomes finding calibration and training approaches that hold up on real parts, in real systems, across the full operating envelope.

Then there's the second problem, which is doing all of that fast. A characterization flow that works in the lab is not a production flow. Getting from one to the other, reliably and on schedule, is its own engineering challenge.

And then there's DVFS, which is a beast in its own right. Validating frequency and voltage transitions without giving up stability or power targets means chasing failures that only appear at specific transition boundaries under specific conditions.

If that sounds like the kind of problem you want to spend your time on, this role has a steady supply of them. It also comes with real visibility: the data you produce goes to the architects planning the next generation, the field teams supporting customers today, and the validation teams qualifying silicon tomorrow. The decisions you influence show up in shipping products.

• The base salary range is $152,000 - $179,000. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.
• We also offer new-hire RSU grants and the opportunity for annual RSU grants, as well as other highly competitive benefits.