Memory Systems Validation Engineer — Calibrate LPDDR5/6 at Speed

AMC OU Ambarella Corp; United States; On-site; USD 152,000 - 179,000; Full time

Job summary

Ambarella seeks an engineer to own the memory subsystem for our AI Vision Processors. You will lead memory training, calibration code, and automation, spending time in the lab for silicon bring-up and writing scalable tests to catch issues early.

You will analyze lab data, drive root causes with field teams and customers, and help shape next-generation memory controllers. Strong collaboration and data-driven insight are essential for robust, high-speed LPDDR5/5X/6 operation.

Qualifications

• 4+ years in memory validation, memory controller design, SoC validation, or closely related area.
• Hands-on experience with LPDDR5/5X and LPDDR6, and working familiarity with JEDEC specifications.
• Experience owning or contributing to memory training and calibration code, with the C/firmware skills to maintain it.
• Strong Python for test automation and data analysis.
• Practical debug skills on real hardware: bench instrumentation, protocol analyzers, logic analyzers, boot and stability failure triage.
• Comfort with data at scale — you can take a pile of shmoo, margining, or regression results and find the signal in it.
• Ability to work directly with customers and cross-functional teams under time pressure.

Responsibilities

• Own the memory training and calibration code.
• You’ll develop, maintain, and tune the training and calibration routines that get LPDDR5/5X and LPDDR6 running reliably at speed across parts, boards, and operating conditions.
• Collect and analyze memory subsystem data from lab testing, customer platforms, and internal validation systems.
• Build automation for memory stability testing, performance characterization, speed binning, and regression analysis — expanding test coverage while cutting cycle time.
• Debug real customer issues alongside field teams and internal engineering groups, driving problems from first report to root cause to closure.
• Turn system behavior and failure analysis into insight that measurably improves memory controller robustness and performance.
• Influence future silicon. Propose architectural and design enhancements for next-generation memory controllers, backed by empirical data, customer feedback, and field experience.
• Validate power-saving features, characterizing them against performance, reliability, and power targets across a wide range of real-world use cases.
• Support silicon bring-up, qualification, and production readiness for memory subsystems.

Skills

Memory validation

Memory controller design

SoC validation

C/firmware programming

Python for test automation

Data analysis

Customer interaction

Hardware debugging

Tools

LPDDR5/5X

LPDDR6

JEDEC specifications

Bench instrumentation

Logic analyzers

Oscilloscope

Protocol analyzers

Job description

Ambarella seeks an engineer to own the memory subsystem for our AI Vision Processors. You will lead memory training, calibration code, and automation, spending time in the lab for silicon bring-up and writing scalable tests to catch issues early.

You will analyze lab data, drive root causes with field teams and customers, and help shape next-generation memory controllers. Strong collaboration and data-driven insight are essential for robust, high-speed LPDDR5/5X/6 operation.