DDR Memory Interface System Validation Lead Engineer

Altera; San Jose (CA); On-site; USD 149,100 - 215,000; Full time

Job summary

Altera in San Jose is seeking a highly skilled DDR5 / LPDDR5 Memory Validation Engineer to lead validation and debug activities for advanced memory interfaces on cutting-edge FPGA devices.

The role requires significant industry experience in memory subsystem validation and strong collaboration skills across multiple teams. The salary range is $149,100 - $215,000 USD, with additional incentive opportunities.

Qualifications

• Minimum of 8+ years of industry experience in memory subsystem validation or high-speed interface validation.
• Experience with DDR5 and LPDDR5 memory technologies.
• Ability to collaborate with cross-functional teams across architecture, silicon design, and firmware.

Responsibilities

• Own DDR5 and LPDDR5 memory subsystem validation.
• Create and execute validation plans and strategies.
• Analyze timing behavior and perform compliance checks.
• Debug issues involving memory subsystems and collaborate on design implementation.

Skills

Memory subsystem validation

High-speed interface validation

Debugging

Signal integrity analysis

Education

Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field

Tools

Protocol analyzers

Oscilloscopes

Logic analyzers

Job description

## DDR Memory Interface System Validation Lead EngineerApplylocations: San Jose, California, United Statestime type: Full timeposted on: Posted Yesterdayjob requisition id: R02493# **Job Details:**### ## **Job Description:****About Altera**At AlteraTM, our independence as the world’s largest pure‐play FPGA solutions provider gives us the focus, speed, and agility to innovate without compromise. With more than four decades of industry‐leading FPGA expertise, our singular mission is to deliver the programmable technologies that help customers differentiate, innovate, and scale across rapidly evolving markets like AI, cloud, networking, and edge. As an independent company, we move faster, invest deeper, and partner more closely—empowering our teams to drive breakthrough innovation and shape the future of the FPGA industry.**About the Role**We are seeking a highly motivated and experienced DDR5 / LPDDR5 Memory Validation Engineer to join our Silicon and Platform Validation organization. In this role, you will drive validation, characterization, and debug activities for advanced DDR5 and LPDDR5 memory interfaces on next-generation FPGA devices.You will work closely with architecture, silicon design, board design, firmware, signal integrity, and software teams to ensure industry-leading quality, reliability, performance, and interoperability across memory subsystems and high-speed I/O platforms.This position offers the opportunity to work hands-on with cutting-edge memory technologies, advanced PHY architectures, and high-speed validation infrastructure while influencing future FPGA platform capabilities and validation methodologies.**Key Responsibilities*** Own DDR5 and LPDDR5 memory subsystem validation, including defining and executing validation strategies across multiple FPGA programs.* Create, define, and develop comprehensive system-level validation environments and test suites for advanced memory interface validation.* Perform pre-silicon and post-silicon functional and electrical validation of DDR5 and LPDDR5 controllers, PHYs, and associated high-speed interfaces.* Develop and execute validation plans covering: + Memory initialization and training + Read/write functional validation + System margining and stress testing + Frequency scaling + Memory controller features validation + Stability and reliability validation + Error injection and recovery testing* Perform timing characterization, compliance checks, interoperability testing, and performance validation according to JEDEC specifications.* Analyze signal integrity and timing behavior for high-speed memory interfaces, including eye diagrams, jitter, and timing margins.* Debug complex silicon, firmware, board-level, and system-level issues involving memory subsystems and PHY behavior.* Collaborate with hardware board design teams on high-speed memory channel implementation, including: + Stack-up reviews + Routing strategies + SI/PI considerations + Memory topology optimization + Termination and power delivery schemes* Review schematics, layouts, and board design guidelines for DDR5 and LPDDR5 implementations.* Utilize industry-standard protocol analyzers, oscilloscopes, logic analyzers, and traffic generators for debug and characterization.* Develop, standardize, and maintain validation methodologies, automation frameworks, and measurement flows to improve validation scalability and efficiency.* Partner with silicon design, package, board, firmware, and software teams to drive root-cause analysis and issue resolution.* Collaborate with pre-silicon validation teams to improve post-silicon coverage and future debug capabilities.* Drive innovation in validation infrastructure, automation, and platform enablement to improve throughput and test coverage.**Salary Range**The pay range below is for Bay Area California only. Actual salary may vary based on a number of factors including job location, job-related knowledge, skills, experiences, trainings, etc. We also offer incentive opportunities that reward employees based on individual and company performance. **$149,100 - $215,000 USD**We use artificial intelligence to screen, assess, or select applicants for the position. Applicants must be eligible for any required U.S. export authorizations.#MD-1### ## **Qualifications:****Minimum Qualifications*** Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Electronics Engineering, or related field.* Minimum of 8+ years of industry experience in memory subsystem validation, silicon validation, or high-speed interface validation.### ## **Job Type:**Regular### ## **Shift:**Shift 1 (United States of America)### ## **Primary Location:**San Jose, California, United States### ## **Additional Locations:**### ## **Posting Statement:**All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.**About Altera**Altera: Accelerating InnovatorsAltera provides leadership programmable solutions that are easy-to-use and deploy in applications from cloud to edge, offering limitless AI possibilities. Our end-to-end broad portfolio of products including FPGAs, CPLDs, Intellectual Property, development tools, System on Modules, SmartNICs and IPUs provide the flexibility to accelerate innovation. Altera is helping to shape the future through pioneering innovation that unlocks extraordinary possibilities for everyone on the planet.