ASIC and Logic Design Engineering Manager (Compute Test, North Reading)

Teradyne; North Reading (MA); On-site; USD 156,000 - 249,000; Full time

Benefits offered by this job

Health benefits

Tuition assistance

Paid vacation

Job summary

Teradyne in North Reading, MA, seeks an ASIC and Logic Design Engineering Manager to lead a 4–6 person FPGA/ASIC team for Compute Test products. You will oversee 2–3 FPGA/digital IP projects, collaborate across disciplines, and ensure timely deliverables in budget.

The role requires RTL coding, strong leadership, and experience with Vivado/Quartus, Cadence, clocking constraints, and high‑volume hardware development. Excellent communication skills are essential.

Qualifications

• BSEE or MSEE with 12+ years in Digital FPGA design and integration.
• 5+ years as FPGA/ASIC project lead.
• Experience coding RTL (Verilog).
• Cadence or similar digital simulation tools experience.
• Experience with static timing analysis tools.
• Experience with PCIe, DDR3/4/5, AXI, Ethernet, SPI, SERDES.
• Experience with AMD or Altera FPGAs and tools (Vivado/Quartus).
• Experience with LINT/CDC and bug-tracking tools (Jira).
• Source control experience (Clearcase, Git, CVS) and CI.
• Familiarity with UVM and project scheduling tools.
• Embedded processors and DSP experience a plus.
• C/C++ a plus.
• Excellent presentation and communication skills.
• 2–3 years first-level engineering management experience a plus.
• Hardware for automated test equipment development a plus.

Responsibilities

• Lead multiple FPGA or digital IP development projects.
• Plan and track project schedule and budget.
• Manage staffing levels including full-time and contract resources.
• Collaborate with other disciplines to satisfy product requirements.
• Contribute to FPGA implementation with RTL code as needed.
• Provide technical support for hardware sustaining issues.
• Set goals and coach a 4–6 person team; manage compensation.
• Represent FPGA team on program reviews and core teams.
• Drive FPGA team process improvements.

Skills

Verilog RTL

FPGA design

Project leadership

C/C++

Education

BSEE or MSEE

Tools

Vivado

Quartus

Jira

Git

ClearCase

Job description

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ASIC and Logic Design Engineering Manager (Compute Test, North Reading)

Date: Aug 28, 2026

Location: North Reading, MA, US

We are the global test and automation specialists, powering next-generation technologies through sophisticated solutions. Behind every electronic device you use, Teradyne's test technology ensures your device works right the first time, every time! Our portfolio of automation solutions help manufacturers to develop and deliver products quickly, efficiently and cost-effectively. Together,Teradyne companies deliver manufacturing automation across industries and applications around the world!

We attract, develop, and retain a high-performance workforce, comprised of people with diverse backgrounds and a shared drive for excellence. We strive to foster a positive and inclusive work environment that helps employees, and communities, thrive.

Our Purpose

TERADYNE, where experience meets innovation and driving excellence in every connection. We are fueled by creativity and diversity of thought and in our workforce. Our employees are supportedto innovate and learn something new every day.
We cultivate a culture of inclusion for all employees that respects their individual strengths, views, and experiences. We believe that our differences enable us to be a better team - one that makes better decisions, drives innovation and delivers better business results.

Opportunity Overview

TheLogicDesign Managerisresponsible forleading a team of developersindesigning and verifyingFPGA’sfor TeradyneComputeTest Division’s nextgenerationproducts.In this role you willlead a team of~4-6engineers in a fast-paced environmenttohelp the organizationmeet key business needs.Requires closecollaborationwiththeotherFPGA design and verification managers and with otherengineeringdisciplinesincludingmixed signalASIC design,circuit board design,softwareand systemsengineeringtospecify andimplementnew products.You should have hands-on experience with complexFPGA(and preferably digitalASIC)SOC designs for real-world products. Youalso shouldhave a proventrack recordof managing engineering teams towardtimelydeliverables and successful project completion.

Leadmultiple simultaneous(typically 2-3) FPGA or digital IP development projects.

Typically includes oversight of some remote resources.

Planning and trackingofproject scheduleandbudget.

Manage project staffing levelsincluding bothfull time and contract resources.

Represent theFPGAteam on project core teamsand atprogram reviews.

Contribute to FPGA implementation (i.e.code RTL blocks) as needed.

Provide technical supportfor HWsustainingissues.

Set goals, provide coaching and manage compensationofa4-6personteam.

Contribute toFPGAteam process improvement initiatives.

Collaborate withother engineering and business disciplines to ensure thatFPGA and IPdeliverablessatisfy all product requirements.

All About You

We seek individuals who share our passion and determination. Our commitment to customer success drives us to go the extra mile. If you're ready to join us in this mission, take a closer look at the minimum criteria for the position.

• BSEEorMSEEand12+ years of relevant experience in DigitalFPGAdesign and integration(DigitalASICexperience is a plus).
• Minimum of 5 years of experience as an FPGA/ASIC project lead, driving multiple projects from concept, architecture exploration, design implementation and lab validation to production release.
• Extensive experience coding RTL(verilogpreferred).
• Extensive experienceusingdigital simulation tools (Cadence preferred).
• Extensive experienceusingstatic timing analysis tools.
• Experience designing with the following: PCIe, DDR3/4/5, AXI, ethernet, SPI, SERDES
• Experience with eitherAMDorAlteraFPGAs anddevelopment tools(Vivado/Quartus), preferably both.
• Experienceusingdigital design qualitytoolse.g.LINT, CDC.
• Experience with bug tracking tools (Jiraetc.)
• Experience with source control systems (Clearcase, Git, CVS) and continuous integration.
• Familiarity with digital verification tools and methodologies (preferably UVM).
• Experience with projectschedulingtools (e.g.Microsoft project)
• Experience with embedded processorsand digital signal processing is a plus.
• Experience with high level programming languages (C, C++) is a plus.
• Excellent presentation and communication skills.
• Preferred: Experience developing hardware for automated test equipment is a plus.
• Preferred: 2-3 years of experience as a first level manager of an engineering team.

Compensation:
The base salary range for this role is $155,500 - $ 248,700. This range is a good faith estimate, and the amount of base salary will correspond with experience and skill set. This range can also fluctuate depending on demand and location.

Incentive Plan:This job is eligible for discretionary bonus(es) based on financial performance.

Teradyne offers a variety of robust health and well-being benefit programs, including medical, dental, vision, Flexible Spending Accounts, retirement savings plans, life and disability insurance, paid vacation & holidays, tuition assistance programs, and more.