Memory Systems Architect — RAS & Telemetry Lead

Samsung Semiconductor Inc.; San Jose (CA); On-site; USD 163,000 - 253,000; Full time

Benefits offered by this job

Charitable giving match

Paid time off 4+ weeks

Fertility/adoption stipend

Medical travel support

Onsite cafe and gym

Flexible benefits

Job summary

Samsung Semiconductor in San Jose is hiring a Staff Engineer, Memory Systems Architecture to advance fault management for data center memory fleets and to lead in-field telemetry development. The role focuses on DRAM/HBM failure modes, ECC schemes, and RAS algorithms to reduce downtime in AI/ML workloads.

You will collaborate with customers, analyze failures, and help standardize logging while driving memory subsystems innovation in a startup-like environment.

Qualifications

• Bachelor's degree with 10+ years of relevant industry experience, or Master's with 8+ years or PhD with 5+ years hardware fault management experience preferred.
• Knowledge of platform memory subsystem and RAS such as ECC, page offlining, hPPR.
• ECC design and verification and reverse engineering experience.
• Understanding the address mapping between CPU and memory.
• Memory controller register modification.
• Linux kernel commit experience.
• DRAM and HBM failure mode understanding.

Responsibilities

• Based on knowledge of SOC controller and memory operation including RAS, recommend solutions to mitigate field DRAM failure rate.
• Communicate ECC schemes to customers based on Samsung DRAM failure mode (DQ and burst).
• Interface with customers to establish the value add of in-field fault management architecture.
• Contribute to standardization of DRAM/HBM failure logging in the OCP.
• Propose and develop platform RAS algorithms and conduct POC with known failure DIMMs in real servers and applications.

Skills

Memory subsystem

RAS features

ECC design

Memory mapping

Linux kernel

DRAM/HBM failure understanding

Education

Bachelor's degree

Master's degree

PhD

Tools

Linux kernel commits

Job description

Samsung Semiconductor in San Jose is hiring a Staff Engineer, Memory Systems Architecture to advance fault management for data center memory fleets and to lead in-field telemetry development. The role focuses on DRAM/HBM failure modes, ECC schemes, and RAS algorithms to reduce downtime in AI/ML workloads.

You will collaborate with customers, analyze failures, and help standardize logging while driving memory subsystems innovation in a startup-like environment.