Custom Memory Lead for High-Performance CPU IP

NUVACORE; Santa Clara (CA); On-site; USD 200,000 - 300,000; Full time

Job summary

Nuvacore seeks a Custom Design Lead to direct the development of high-performance memory IP for next‑gen CPUs. You will guide a small team through schematic, layout, PDV closure, and cross‑functional signoff to ensure PPA targets are met on advanced CMOS nodes.

You will own memory architecture decisions, collaborate with Foundry/CAD/RTL teams, and drive automation and best practices to raise design efficiency and reliability.

Qualifications

• 12+ years in custom memory circuit design (SRAMs, register files).
• Proven transistor-level design experience for memory arrays and cells.
• Experience delivering production-level memory IP through tape-out.

Responsibilities

• Lead a small team of engineers responsible for development of custom memories (SRAM and register files).
• Supervise layout, macro floorplanning, and PDV closure to meet PPA targets.
• Drive end-to-end memory IP signoff (DRC/LVS/antenna, extraction, timing, power, noise) across PVT corners.
• Collaborate with Foundry, CAD, RTL/DFT teams to optimize memories for downstream PPA.
• Define tools, flows and methodologies to raise design efficiency.

Skills

Memory design

Team leadership

PPA optimization

Schematic & PDV

End-to-end signoff

Timing & power modeling

DC/AC parasitic extraction

Education

BS/MS/PhD in related field

Tools

SPICE simulations

EDA tool suite

Liberty/CCS models

Job description

Nuvacore seeks a Custom Design Lead to direct the development of high-performance memory IP for next‑gen CPUs. You will guide a small team through schematic, layout, PDV closure, and cross‑functional signoff to ensure PPA targets are met on advanced CMOS nodes.

You will own memory architecture decisions, collaborate with Foundry/CAD/RTL teams, and drive automation and best practices to raise design efficiency and reliability.