Low-Power HSIO Architect for NVLink Interconnects (Equity Options)

NVIDIA

Town of Texas (WI)

On-site

USD 196,000 - 311,000

Full time

14 days+

Application generator

Stand out for this role — generate a tailored resume and cover letter in about a minute.

Get past ATS filters

Benefits offered by this job

Equity

Benefits package

Job summary

NVIDIA Silicon Co-Design Group is seeking a versatile engineer to join the HW ArchDev team. You will contribute to the design of the next generation of high-speed IOs, including NVLink and NVLink-C2C, and own IO power optimizations across complex interconnect topologies.

This role provides end-to-end exposure from arch through bringup to product release, with collaboration across system architects, mixed-signal and design, DGX, software/firmware, HW/SW QA, operations, and AE teams to drive

Qualifications

BS or MS in EE/CE or equivalent experience.
10+ years working on HSIO with power management, perf/power modeling, bringup, and/or debug.
Ownership and experience in system-level and interconnect power management optimizations, silicon and platform power modeling, firmware/driver interaction.

Responsibilities

Design the next generation of high-speed IOs (NVLink, NVLink-C2C).
Optimize IO power and energy efficiency across interconnects.
Ensure interoperability with devices and components in complex topologies.
Debug HSIO issues across multiple teams and drive resolution.
Collaborate with system architects, mixed-signal/design, DGX, software/firmware, HW/SW QA, operations, and AE teams to drive design and release.