HSIO Power & Interconnect Engineer — Bringup & Debug

NVIDIA

Oregon (WI)

On-site

USD 168,000 - 311,000

Full time

14 days+

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Job summary

NVIDIA Silicon Co-Design Group seeks a versatile engineer for the HW ArchDev team to influence the next generation of high-speed interconnects and system-level features. You will work on NVLink and NVLink-C2C, focusing on energy efficiency, cross-team collaboration, and robust bringup through product release.

The role requires 10+ years in HSIO with power management and performance modeling, and a track record of leadership across multiple teams.

Qualifications

10+ years working on HSIO with power management, use case analysis, perf/power modeling, bringup, or debug.
Experience with system-level and interconnect power management optimizations.
Silicon and platform-level power modeling for active/idle use cases.

Responsibilities

Contribute to the design of the next generation of high-speed IOs, including NVLink and NVLink-C2C.
Responsible for IO power optimizations and continuing to push energy efficiency.
Ensure interoperability with connected devices and system components in complex interconnect topologies
Deep dive into technically challenging HSIO bugs and help drive debug efforts across various teams
Work closely and proactively with other engineering teams to drive design, development, debug, and release of next-generation products.