Low-Power HSIO Architect for Next-Gen NVLink – Equity

NVIDIA Gruppe; Santa Clara (CA); Hybrid; USD 168,000 - 311,000; Full time

Benefits offered by this job

Equity

Job summary

NVIDIA Silicon Co-Design Group is seeking a seasoned engineer for the HW ArchDev team. You will contribute to the design of the next generation of high-speed IOs (NVLink/NVLink-C2C) and own IO power optimization across complex interconnect topologies.

With 10+ years on HSIO and strong EE fundamentals, you will lead cross-team efforts to bring bringup, debug, and release of future NVIDIA products. This hybrid role in Santa Clara offers equity and broad benefits.

Qualifications

• BS or MS in EE/CE or equivalent experience.
• 10+ years working on HSIO with power management, perf/power modeling, bringup, or debugging.
• Leadership and collaboration across multiple teams toward a common goal.
• Strong fundamentals in computer architecture, high-speed interfaces, timing and power analysis.

Responsibilities

• Design next generation high-speed IOs, including NVLink and NVLink-C2C.
• Optimize IO power and push energy efficiency.
• Ensure interoperability with system components in complex interconnects.
• Investigate HSIO bugs and drive debugging across teams.
• Collaborate with system architects, design, firmware, QA, and operations to drive release.

Skills

EE fundamentals

Computer architecture

High-speed interfaces

Timing analysis

Power analysis

Leadership

Collaboration

Education

BS or MS in EE/CE

Tools

Firmware/Driver concepts

Job description

NVIDIA Silicon Co-Design Group is seeking a seasoned engineer for the HW ArchDev team. You will contribute to the design of the next generation of high-speed IOs (NVLink/NVLink-C2C) and own IO power optimization across complex interconnect topologies.

With 10+ years on HSIO and strong EE fundamentals, you will lead cross-team efforts to bring bringup, debug, and release of future NVIDIA products. This hybrid role in Santa Clara offers equity and broad benefits.