Senior HSIO Architect: Low-Power Interconnects & NVLink

NVIDIA; Washington; On-site; USD 168,000 - 311,000; Full time

Benefits offered by this job

Equity

Benefits package

Job summary

NVIDIA Silicon Co-Design Group is seeking a versatile engineer for the HW ArchDev team. The role covers end-to-end product development from arch definition to release, focusing on HPIO like NVLink and NVLink-C2C.

You will own power optimizations, system-level thinking, and cross-team collaboration to push energy efficiency and reliable interconnects across AI, graphics, and autonomous platforms.

Qualifications

• BS or MS degree in EE/CE or equivalent experience.
• Minimum 10 years working on HSIO including power management, use case analysis, perf/power modeling, bringup, and/or debug.

Responsibilities

• Design next-gen high-speed IOs (NVLink, NVLink-C2C).
• Optimize IO power and energy efficiency.
• Ensure interoperability within complex interconnects.

Skills

Power management

HSIO experience

System-level thinking

Cross-team collaboration

High-speed interfaces

Education

BS/MS in EE/CE

Job description

NVIDIA Silicon Co-Design Group is seeking a versatile engineer for the HW ArchDev team. The role covers end-to-end product development from arch definition to release, focusing on HPIO like NVLink and NVLink-C2C.

You will own power optimizations, system-level thinking, and cross-team collaboration to push energy efficiency and reliable interconnects across AI, graphics, and autonomous platforms.