HSIO Power & Interconnect Engineer (NVLink)

NVIDIA; Santa Clara (CA); Hybrid; USD 168,000 - 311,000; Full time

Benefits offered by this job

Equity

Benefits

Job summary

NVIDIA Silicon Co-Design Group seeks a versatile engineer for the HW ArchDev team. You will contribute to the design and bringup of next-generation high-speed interconnects, including NVLink and NVLink-C2C, while driving energy efficiency and system interoperability across multiple NVIDIA product lines.

You will collaborate with system architects, mixed-signal and design teams, DGX, software/firmware, QA, operations and AE to move designs from concept to release, addressing challenging HSIO bugs

Qualifications

• BS or MS in EE/CE or equivalent
• 10+ years working on HSIO (power mgmt, perf/power modeling, bringup, debug)
• Ownership of HSIO areas such as power management, use case analysis, and debug

Responsibilities

• Design the next generation of high-speed IOs (NVLink, NVLink-C2C)
• Optimize IO power and energy efficiency
• Ensure interoperability across complex interconnect topologies
• Debug HSIO bugs and drive cross-team debugging efforts
• Collaborate with system architects, DGX, software/firmware, QA, operations and AE teams to release next-gen products

Skills

Power management

HSIO design

Debugging

Cross-team collaboration

Education

BS/MS in EE or CE

Job description

NVIDIA Silicon Co-Design Group seeks a versatile engineer for the HW ArchDev team. You will contribute to the design and bringup of next-generation high-speed interconnects, including NVLink and NVLink-C2C, while driving energy efficiency and system interoperability across multiple NVIDIA product lines.

You will collaborate with system architects, mixed-signal and design teams, DGX, software/firmware, QA, operations and AE to move designs from concept to release, addressing challenging HSIO bugs