Low-Power Edge AI SoC Physical Design Intern

Ambarella; Kentucky; Sur place; USD 120 000 - 170 000; Plein temps

Résumé du poste

Ambarella is seeking a Physical Design Engineer to drive the physical design implementation and verification of our low-power AISoC from netlist to GDSII. You will contribute across floor-planning, auto place and route, static timing analysis, ECOs, signal integrity, EM/IR checks, formal verification and layout verification at block and full-chip levels.

Responsibilities include ensuring performance, power and area targets while maintaining design rules and quality gates.

Qualifications

• The Physical Design Engineer will handle all aspects of SoC physical design implementation and verification.
• Key tasks include floor-planning, auto place and route, timing analysis, eco implementation, SI/EM/IR checks, formal verification and LVS/DRC/DFM at block or full-chip level.

Responsabilités

• Oversee end-to-end physical design flow for Ambarella’s low power AISoc from netlist to GDSII.

Connaissances

Floor-planning

Place & route

Static timing

Eco implementation

Signal integrity

EM/IR analysis

Formal verification

LVS/DRC/DFM

Description du poste

Ambarella is seeking a Physical Design Engineer to drive the physical design implementation and verification of our low-power AISoC from netlist to GDSII. You will contribute across floor-planning, auto place and route, static timing analysis, ECOs, signal integrity, EM/IR checks, formal verification and layout verification at block and full-chip levels.

Responsibilities include ensuring performance, power and area targets while maintaining design rules and quality gates.