Physical Design Engineer Intern

Ambarella; Kentucky; On-site; USD 120,000 - 170,000; Full time

Job summary

Ambarella is seeking a Physical Design Engineer to drive the physical design implementation and verification of our low-power AISoC from netlist to GDSII. You will contribute across floor-planning, auto place and route, static timing analysis, ECOs, signal integrity, EM/IR checks, formal verification and layout verification at block and full-chip levels.

Responsibilities include ensuring performance, power and area targets while maintaining design rules and quality gates.

Qualifications

• The Physical Design Engineer will handle all aspects of SoC physical design implementation and verification.
• Key tasks include floor-planning, auto place and route, timing analysis, eco implementation, SI/EM/IR checks, formal verification and LVS/DRC/DFM at block or full-chip level.

Responsibilities

• Oversee end-to-end physical design flow for Ambarella’s low power AISoc from netlist to GDSII.

Skills

Floor-planning

Place & route

Static timing

Eco implementation

Signal integrity

EM/IR analysis

Formal verification

LVS/DRC/DFM

Job description

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Job Description

The Physical Design Engineer willbe an integral part of the physical design team with all aspects of physical design implementation and verification tasks for Ambarella’s cutting edgelow powerAISoC from Netlist to GDSII.

The Physical Design Engineer will be responsible for the following areas throughout all phase of SoC implementation process; floor-planning, auto place and route, static timing analysis, eco implementation, signal integrity analysis, EM/IR analysis, formal verification, and physical layout verification (LVS/DRC/DFM) at block and/or full chip level.