Low-Power AI SoC Physical Design Intern

Ambarella; Headquarters (ID); On-site; USD 120,000 - 180,000; Full time

Job summary

Ambarella is seeking a Physical Design Engineer to contribute to the physical design and verification of our low-power AI SoC. You will be involved from netlist to GDSII, handling floorplanning, auto place and route, timing analysis, eco implementation, and SI/EM/IR analyses.

This role supports LVS/DRC/DFM checks at block or chip level and collaborates across teams to deliver high-quality silicon for autonomous systems, surveillance, drones and smart cameras.

Qualifications

• Bachelor's or Master's degree in Electrical/Computer Engineering or related field.

Responsibilities

• Contribute to all phases of SoC physical design implementation and verification.
• Perform floorplanning, auto place and route, and physical layout verification (LVS/DRC/DFM).
• Conduct static timing analysis and eco implementation.
• Analyze signal integrity and EM/IR effects.
• Support formal verification and block/full-chip checks.

Skills

Floorplanning

Place & Route

Static Timing Analysis

Physical Verification

Signal Integrity

Job description

Ambarella is seeking a Physical Design Engineer to contribute to the physical design and verification of our low-power AI SoC. You will be involved from netlist to GDSII, handling floorplanning, auto place and route, timing analysis, eco implementation, and SI/EM/IR analyses.

This role supports LVS/DRC/DFM checks at block or chip level and collaborates across teams to deliver high-quality silicon for autonomous systems, surveillance, drones and smart cameras.