Edge AI SoC Physical Design Engineer Intern

VisLab (an Ambarella Inc. company); Kentucky; On-site; USD 110,000 - 170,000; Full time

Job summary

VisLab (an Ambarella Inc. company) is seeking a Physical Design Engineer to join the design team and carry out physical design implementation and verification for Ambarella’s cutting edge low power AI SoC from Netlist to GDSII.

The engineer will contribute across all phases of the SoC flow. Key duties include floor-planning, auto place and route, static timing analysis, ECO implementation, signal integrity analysis, EM/IR analysis, formal verification, and physical layout verification

Responsibilities

• floor-planning
• auto place and route
• static timing analysis
• eco implementation
• signal integrity analysis
• EM/IR analysis
• formal verification
• physical layout verification (LVS/DRC/DFM) at block and/or full chip level.

Job description

VisLab (an Ambarella Inc. company) is seeking a Physical Design Engineer to join the design team and carry out physical design implementation and verification for Ambarella’s cutting edge low power AI SoC from Netlist to GDSII.

The engineer will contribute across all phases of the SoC flow. Key duties include floor-planning, auto place and route, static timing analysis, ECO implementation, signal integrity analysis, EM/IR analysis, formal verification, and physical layout verification