Lead Verification Architect - Silicon Photonics

Cisco Systems, Inc; Allentown (Lehigh County); On-site; USD 192,000 - 276,000; Full time

Job summary

Cisco Systems, Inc. seeks a Design Verification Technical Leader to drive verification across high-speed silicon photonics drivers and related IPs.

You will direct block- and chip-level verification, mentor engineers, and influence testability strategies, enabling scalable, reliable silicon for data center platforms. The role emphasizes cross-site coordination, architecture input, and hands-on debugging of complex issues during bring-up while shaping verification for next-generation 800G/1.6T

Qualifications

• Bachelor’s degree in Electrical or Computer engineering with 8+ years ASIC design verification.
• Master’s degree in Electrical/Computer Eng or Computer Eng with 6+ years ASIC verification experience; PhD +3 years acceptable.
• Experience in SystemVerilog, UVM, and verification methodologies.

Responsibilities

• Define and lead verification methodology and standards across multiple projects, coordinating activities across sites.
• Mentor and coach verification engineers, driving continuous improvement in skills and execution.
• Lead verification at block and chip level with high-speed IPs integrated like ODSP, D2D IP, SerDes XSR/PAM4, and testability features.
• Review specifications, participate in design reviews, and influence architecture for testability and efficiency.
• Debug complex silicon and system-level issues during bring-up phases and support post-silicon bring-up.

Skills

SystemVerilog

UVM

Verification methodologies

Team leadership

Python scripting

Education

Bachelor’s in Electrical or Computer Eng

Master’s in Electrical or Computer Eng

PhD in Electrical/Computer Eng

Tools

Veloce

HAPS

Job description

Cisco Systems, Inc. seeks a Design Verification Technical Leader to drive verification across high-speed silicon photonics drivers and related IPs.

You will direct block- and chip-level verification, mentor engineers, and influence testability strategies, enabling scalable, reliable silicon for data center platforms. The role emphasizes cross-site coordination, architecture input, and hands-on debugging of complex issues during bring-up while shaping verification for next-generation 800G/1.6T