Senior Manager, SoC Verification & TPU Methodology

Google; Sunnyvale (CA); On-site; USD 240,000 - 333,000; Full time

Job summary

Google in Sunnyvale is seeking a Senior Manager for SoC Design Verification and Methodology to shape TPU verification strategies and drive cutting-edge silicon development.

You will lead a team responsible for functional verification of TPU components, develop scalable verification flows across subchip to full-chip levels, and partner with front-end design, architecture, and performance teams to ensure architectural compliance and performance objectives.

Qualifications

• Bachelor's degree or equivalent practical experience in EE/CE/CS.
• 15 years of experience with SOC design verification, SystemVerilog, and UVM.
• 6 years of people management experience.

Responsibilities

• Lead a team of individuals; set and communicate individual and team priorities that support organizational goals.
• Define and drive advanced verification methodologies and strategies, including simulation for bug hunts, formal verification for corner-case bugs, and emulation for system validation.
• Guide the functional verification team for portions of TPU designs, developing scalable functional verification infrastructure across subchip, subsystem, and full-chip level environments.
• Partner with front-end design, architecture, and performance teams to help ensure architectural compliance and the achievement of performance goals.
• Provide test plans, including verification strategy, environment, components, stimulus, checks, and coverage, ensuring that methodology documentation is standardized and easy to use.

Skills

SOC design verification

People management

Education

Bachelor's degree in Electrical Engineering / Computer Engineering / Computer Science

Master's degree or PhD (preferred)

Tools

SystemVerilog

UVM

Job description

Google in Sunnyvale is seeking a Senior Manager for SoC Design Verification and Methodology to shape TPU verification strategies and drive cutting-edge silicon development.

You will lead a team responsible for functional verification of TPU components, develop scalable verification flows across subchip to full-chip levels, and partner with front-end design, architecture, and performance teams to ensure architectural compliance and performance objectives.