Lead Space Hardware Engineer: FPGA & High-Speed Digital

Viasat; Tempe, Northern (AZ, KY); Hybrid; USD 133,000 - 247,000; Full time

Job summary

Viasat is seeking a senior hardware engineer to lead the design of high-speed digital boards for space applications in Tempe, AZ. You will define FPGA architecture, SoC integration, and mixed-signal interfaces, guiding a multidisciplinary team through full hardware development lifecycle.

The role requires hands-on debugging, strong signal integrity analysis, and experience with DDR4, SERDES, UART, and SPI. US citizenship and travel up to 10% are required.

Qualifications

• Bachelor’s degree in Electrical Engineering or related field.
• 6+ years of hardware engineering experience with high-speed digital boards.
• Experience with FPGA architecture and SoC integration.
• Space/flight hardware design experience and qualification processes.
• Experience with Mentor Xpedition or Cadence for schematic capture.

Responsibilities

• Lead schematic capture and board-level design for high-speed digital hardware in space applications.
• Define and drive FPGA architecture and SoC integration across the hardware platform.
• Design high-speed interfaces (DDR4, SERDES, UART, SPI).
• Perform power/signal integrity analysis and implement corrective design changes.
• Lead a multidisciplinary engineering team through hardware development milestones and reviews.
• Collaborate with firmware and software teams for co-design and integration.
• Support board bring-up, integration, and debug in the lab.

Skills

High-speed digital design

FPGA architecture

SoC integration

Troubleshooting

Team leadership

Schematic capture

DDR4 interfaces

Serdes

UART

SPI

Communication skills

US citizenship

Travel readiness

Education

Bachelor Degree in Electrical Engineering

MS EE preferred

Tools

Mentor Xpedition

Cadence

HyperLynx

Job description

Viasat is seeking a senior hardware engineer to lead the design of high-speed digital boards for space applications in Tempe, AZ. You will define FPGA architecture, SoC integration, and mixed-signal interfaces, guiding a multidisciplinary team through full hardware development lifecycle.

The role requires hands-on debugging, strong signal integrity analysis, and experience with DDR4, SERDES, UART, and SPI. US citizenship and travel up to 10% are required.