Senior Space FPGA Engineer: Signal Processing & RTL

Medium; Saratoga (CA); On-site; USD 100,000 - 200,000; Full time

Job summary

E-Space is hiring a Staff Satellite FPGA Engineer - Signal Processing to lead FPGA RTL development for LEO satellites from concept to flight. You will architect digital hardware interfaces, perform timing analyses, and drive verification across simulations, benches, and tests.

The role requires 10+ years in FPGA RTL, SystemVerilog or VHDL, and experience with space environments. Location is Saratoga, CA; base salary range is $100,000–$200,000 with full benefits and growth opportunities.

Qualifications

• 10+ years of experience in FPGA RTL architecture, development, verification, deployment and maintenance.
• Proficiency with SystemVerilog or VHDL.
• Proficiency in at least one scripting language (TCL, shell, Python).
• Experience with verification techniques, timing and stability analysis.
• Understanding of PCB designs and schematics.
• Understanding embedded software.
• Knowledge of ADC/DAC interfaces and JESD204.
• Experience with high-speed digital communications interfaces.
• Ability to work in a dynamic environment.

Responsibilities

• Own FPGA RTL development from blank sheet to flight in SystemVerilog or VHDL.
• Define HW/SW interfaces and FPGA subsystem architecture.
• Implement digital channelizer beamformer from reference models.
• Drive part selection and PCB architecture.
• Perform design verification including simulations and hardware testing.
• Lead design reviews and maintain requirement traceability.
• Develop and participate in test campaigns at multiple levels.

Skills

FPGA RTL

SystemVerilog

VHDL

scripting languages

verification

PCB understanding

embedded software

JESD204

high-speed interfaces

lead reviews

Education

Master’s degree in Engineering

space environments experience

Tools

Model Based Design

SystemRDL

Job description

E-Space is hiring a Staff Satellite FPGA Engineer - Signal Processing to lead FPGA RTL development for LEO satellites from concept to flight. You will architect digital hardware interfaces, perform timing analyses, and drive verification across simulations, benches, and tests.

The role requires 10+ years in FPGA RTL, SystemVerilog or VHDL, and experience with space environments. Location is Saratoga, CA; base salary range is $100,000–$200,000 with full benefits and growth opportunities.