Lead SoC Verification Architect for AI Infrastructure

Asteralabs; San Jose (CA); On-site; USD 185,000 - 230,000; Full time

Benefits offered by this job

Discretionary bonus

Competitive compensation

Benefits

Job summary

Astera Labs in San Jose, CA seeks a Principal Design Verification Engineer to lead functional verification of advanced SoCs for server and networking applications. You will drive test planning, development, and coverage closure across the full verification lifecycle.

You should have 8+ years of SoC verification experience, strong SystemVerilog/UVM expertise, and hands-on scripting with Python or C/C++. The role offers a competitive salary and potential discretionary bonuses.

Qualifications

• Bachelor’s degree in Electrical Engineering (Master’s preferred).
• 8+ years of experience in SoC verification for server and networking applications.
• Expertise in SystemVerilog/UVM and full verification lifecycle.
• Proficiency with industry-standard simulators, version control, and regression systems.
• Strong debugging and coverage analysis skills.
• Experience with test sequences, stimuli, and verification holes.

Responsibilities

• Lead the functional verification of advanced ASICs, including test planning, development, execution, and coverage analysis.
• Collaborate with software and system validation teams to create and execute test plans on emulation platforms.
• Apply directed and constrained-random verification techniques using SystemVerilog/UVM and other tools.
• Debug test failures, analyze coverage results, and close functional coverage gaps.
• Work with RTL designers to troubleshoot and resolve design issues.
• Drive verification strategy and methodology for SoCs in server and networking applications.

Skills

SystemVerilog/UVM

Debugging

Coverage analysis

Independent work

Education

Bachelor’s degree in Electrical Engineering

Master’s preferred

Tools

Industry-standard simulators

Version control

Regression systems

Job description

Astera Labs in San Jose, CA seeks a Principal Design Verification Engineer to lead functional verification of advanced SoCs for server and networking applications. You will drive test planning, development, and coverage closure across the full verification lifecycle.

You should have 8+ years of SoC verification experience, strong SystemVerilog/UVM expertise, and hands-on scripting with Python or C/C++. The role offers a competitive salary and potential discretionary bonuses.