Founding Design Verification Lead for AI-Driven SoCs

Architect Labs; Palo Alto (CA); On-site; USD 210,000 - 320,000; Full time

Benefits offered by this job

Competitive salary

Meaningful equity stake

Autonomy and visible impact

Cutting-edge AI and silicon challenges

Job summary

Architect Labs is seeking a Founding Member of the Technical Staff to lead the Design Verification efforts for AI-driven design automation. You will own the verification strategy for AI-generated designs taping out on leading foundries and collaborate across hardware and AI teams.

This role combines hands-on DV with leadership, enabling scalable validation across IPs, emulation, and FPGA prototyping, in a fast-paced startup environment in Palo Alto.

Qualifications

• Degree in Electrical Engineering, Computer Engineering, or closely related field.
• 5+ years tapeout experience on advanced-node designs; 10+ preferred.
• DV expertise in verification, emulation, and IP/SoC validation platforms.
• Strong coding in SystemVerilog, UVM, C/C++, Python preferred.
• Hands-on with ARM AMBA, CPU subsystems, memory controllers, NoC.

Responsibilities

• Review AI-driven test plans and validation strategies for internal and external SoC projects.
• Provide domain expertise to AI/ML teams for architectural and microarchitectural checks, validation modularity, and interfaces.
• Define and coordinate validation and integration flows across multiple IPs with checkpoints and collateral handoffs.
• Collaborate with architecture, design, and AI/ML leads to generate simulation- and emulation-ready collateral.
• Track trends in semiconductor verification and AI-driven design automation to keep methodology cutting-edge.

Skills

SystemVerilog

UVM

Python

C/C++

Problem-solving

Leadership

Education

Bachelor’s/Master’s/PhD in Electrical Engineering or related field

Tools

Xilinx Vivado/Vitis

Emulation Tools

FPGA Prototyping

Simulation

Job description

Architect Labs is seeking a Founding Member of the Technical Staff to lead the Design Verification efforts for AI-driven design automation. You will own the verification strategy for AI-generated designs taping out on leading foundries and collaborate across hardware and AI teams.

This role combines hands-on DV with leadership, enabling scalable validation across IPs, emulation, and FPGA prototyping, in a fast-paced startup environment in Palo Alto.