AI-Driven SoC Verification Architect | Scalable DV Strategy

TylSemi; San Jose (CA); On-site; USD 150,000 - 180,000; Full time

Job summary

TylSemi is looking for a Design Verification Architect in San Jose, CA. The ideal candidate will lead the definition and execution of verification strategies for next-generation SoCs focused on AI, HPC, and Networking applications. A strong background in SystemVerilog and UVM, along with deep expertise in large SoC verification and AI/ML methodologies, is essential. This role emphasizes automation, scalability, and collaboration across design and architecture teams.

Qualifications

• 12+ years of experience in Design Verification with a focus on large SoC verification.
• Proven experience in defining and deploying verification architectures for complex chips.
• Experience with multi-IP integration challenges and high-speed interfaces.

Responsibilities

• Define and drive the overall verification architecture for large-scale SoCs.
• Architect and develop reusable, modular, and portable verification platforms.
• Drive multi-level verification strategies across block-level and full-chip.

Skills

SystemVerilog

UVM

Coverage-driven verification

Assertion-based verification

Portable Stimulus (PSS)

SoC architectures in AI, HPC, or Networking

Strong debugging skills

Education

Bachelor’s/Master’s degree in Electrical Engineering or Computer Engineering

Job description

TylSemi is looking for a Design Verification Architect in San Jose, CA. The ideal candidate will lead the definition and execution of verification strategies for next-generation SoCs focused on AI, HPC, and Networking applications. A strong background in SystemVerilog and UVM, along with deep expertise in large SoC verification and AI/ML methodologies, is essential. This role emphasizes automation, scalability, and collaboration across design and architecture teams.