Lead SoC RTL Design Architect for AI/HPC SoCs

TYLsemi; United States; Hybrid; USD 4,200 - 7,300; Full time

Job summary

TYLsemi in Bengaluru seeks an experienced RTL Designer to craft high-performance, power-efficient RTL for next-gen SoCs and chiplets. You will own micro-architecture and drive IP-level integration across subsystems with strong emphasis on quality and first-pass silicon success.

The role requires deep expertise in Verilog/SystemVerilog, high-speed interfaces like PCIe/CXL and Ethernet, and collaboration with architecture, DV, and firmware teams. Hybrid/on-site work in Bengaluru is expected.

Qualifications

• Bachelor's or Master’s in electrical engineering or related field.
• 8+ years of RTL design and micro-architecture experience.
• Strong HDL skills and knowledge of high-speed protocols.

Responsibilities

• Design and implement high-quality RTL for complex SoC components.
• Own micro-architecture definition and execution for performance blocks.
• Develop scalable designs across IP, subsystem, and SoC integration.
• Integrate high-speed IO protocols such as PCIe, CXL, Ethernet, UCIe.
• Ensure timing closure, power efficiency and area optimization.
• Collaborate with architecture, DV, physical design and firmware.

Skills

RTL design

Micro-architecture

Verilog

SystemVerilog

High-speed IO

Education

Bachelor's/Master's in EE

Tools

FPGA prototyping

Emulation platforms

Synthesis tools

Job description

TYLsemi in Bengaluru seeks an experienced RTL Designer to craft high-performance, power-efficient RTL for next-gen SoCs and chiplets. You will own micro-architecture and drive IP-level integration across subsystems with strong emphasis on quality and first-pass silicon success.

The role requires deep expertise in Verilog/SystemVerilog, high-speed interfaces like PCIe/CXL and Ethernet, and collaboration with architecture, DV, and firmware teams. Hybrid/on-site work in Bengaluru is expected.