Principal SoC RTL Design Engineer

TYLsemi; United States; Hybrid; USD 4,200 - 7,300; Full time

Job summary

TYLsemi in Bengaluru seeks an experienced RTL Designer to craft high-performance, power-efficient RTL for next-gen SoCs and chiplets. You will own micro-architecture and drive IP-level integration across subsystems with strong emphasis on quality and first-pass silicon success.

The role requires deep expertise in Verilog/SystemVerilog, high-speed interfaces like PCIe/CXL and Ethernet, and collaboration with architecture, DV, and firmware teams. Hybrid/on-site work in Bengaluru is expected.

Qualifications

• Bachelor's or Master’s in electrical engineering or related field.
• 8+ years of RTL design and micro-architecture experience.
• Strong HDL skills and knowledge of high-speed protocols.

Responsibilities

• Design and implement high-quality RTL for complex SoC components.
• Own micro-architecture definition and execution for performance blocks.
• Develop scalable designs across IP, subsystem, and SoC integration.
• Integrate high-speed IO protocols such as PCIe, CXL, Ethernet, UCIe.
• Ensure timing closure, power efficiency and area optimization.
• Collaborate with architecture, DV, physical design and firmware.

Skills

RTL design

Micro-architecture

Verilog

SystemVerilog

High-speed IO

Education

Bachelor's/Master's in EE

Tools

FPGA prototyping

Emulation platforms

Synthesis tools

Job description

Role Overview

We are looking for a highly skilled RTL Designer to develop high-performance, scalable, and power-efficient digital designs for next-generation SoCsand Chipletstargeting AI, HPC, and Networking applications. This role requires deepexpertisein RTL design, micro-architecture, and integration of high-speed interfaces, along with a strong focus on quality, performance, and first-time silicon success.

WhatYou’llDo

• Design and implement high-quality RTL for complex SoC components and subsystems

• Own micro-architecture definition and execution for performance-critical blocks

• Develop designs that scale across IP, subsystem, and full SoC integration

• Integrate andoptimizehigh-speed IO protocols such as:

• • PCIe / CXL
• • Ethernet (various speeds)
• • UCIe (chiplet interconnects)

• Ensure robust design practices for:

• • Timing closure
• • Power efficiency
• • Area optimization

• Collaborate closely with architecture, DV, physical design, and firmware teams

• Drive design quality initiatives including lint, CDC, RDC, and formal verification

• Support emulation, prototyping, and silicon bring-up

• Contribute to building reusable design components and IPs across multiple programs

• Leverage automation and AI tools to improve RTL productivity and design quality

WhatWe’reLooking For

• Bachelor’s/Master’s degree in Electrical Engineeringor related field

• 8+ years of relevant experience in RTL design and micro-architecture

• Strongexpertisein:

• • Verilog/SystemVerilog
• • Digital design fundamentals
• • High-performance and low-power design techniques
• • Experience designing for large SoCs in AI, HPC, or Networking domains

• Solid understanding of high-speed IO protocols :UCIe, PCIe, Ethernet

• Experience with multi-clock, high-bandwidth, and latency-sensitive designs

• Strong debugging and problem-solving skills

Good to Have

• Experience with memory interfaces (DDR, HBM, LPDDR)

• Familiarity with coherency protocols and interconnect fabrics

• Exposure to synthesis, STA, and physical design constraints

• Experience with emulation or FPGA prototyping

• Working knowledge ofscripting (Python,Tcl)

Key Attributes

• Strong ownership and attention to detail

• Focus on quality and first-pass silicon success

• Ability to work across teams in a fast-paced environment

• Bias toward scalable, reusable, and clean design

Success in This Role Looks Like

• High-quality RTL with minimal re-spins

• Successful integration into complex SoCs

• Performance, power, and area targets met

• Contribution to reusable IP and design frameworks

Location

Hybrid / On-site – Bengaluru