Lead SOC Design Engineer – Timing Closure & RTL

Jobtailor; San Jose (CA); On-site; USD 180,000 - 240,000; Full time

Job summary

Jobtailor is seeking an experienced SOC design lead to guide timing closure for Palladium and Protium tapeouts. The role involves leading a team on SOC/sub-system implementations, RTL synthesis, floor planning, clock-tree building, and full physical verification.

Candidates should have a BS in Electrical Engineering with substantial experience, proficiency with Cadence tools, experience at advanced nodes (5nm/3nm/2nm) and Linux scripting, and the ability to coordinate FE RTL with BE verification

Qualifications

• BS degree in Electrical Engineering with the required years of experience.
• Experience with Cadence tools: Innovus, Tempus, QRC, Voltus and Pegasus.
• Experience with advanced node technologies (5nm/3nm/2nm) and Linux.

Responsibilities

• Implement, verify, and conduct timing closure to tape out Palladium and Protium SOCs.
• Lead a team to implement SOCs or sub-system chips.
• Work on RTL synthesis and floor planning.
• Build clock trees and perform optimizations.
• Close timing, IR drop and physical verification.
• Review and document designs for taping out.
• Interface with Front End RTL design teams and Back End Verification teams.

Education

BS in Electrical Engineering

Tools

Cadence Innovus

Cadence Tempus

Cadence QRC

Cadence Voltus

Cadence Pegasus

Job description

Jobtailor is seeking an experienced SOC design lead to guide timing closure for Palladium and Protium tapeouts. The role involves leading a team on SOC/sub-system implementations, RTL synthesis, floor planning, clock-tree building, and full physical verification.

Candidates should have a BS in Electrical Engineering with substantial experience, proficiency with Cadence tools, experience at advanced nodes (5nm/3nm/2nm) and Linux scripting, and the ability to coordinate FE RTL with BE verification