Senior Timing Methodology Engineer – SOC/3D Signoff

Socket.dev; Wayne (CA); On-site; USD 144,000 - 230,000; Full time

Job summary

Broadcom is seeking an experienced Timing Sign-Off engineer to join the Central Engineering Timing Sign-Off group. The role focuses on developing and deploying timing sign-off methodologies for advanced technology nodes and leading complex SOC/3D/2.5D IC timing initiatives.

You will collaborate across teams, own simulations, and mentor others while delivering high-yield solutions on time. Proficiency with STA tools (Primetime/Tempus) and scripting (TCL/Python) is required, with tapeout

Qualifications

• BS in EE/CS with 12+ years of industry experience or MS/PhD with 10+ years.
• Strong hands-on experience in Timing Signoff methodology development and ownership.
• Strong hands-on experience in SOC and 3D/2.5D IC timing signoff.
• Strong hands-on experience with statistical data analysis and modeling.
• Strong hands-on experience with silicon technologies, testability and yield.
• Experience with Primetime, Tempus, and Innovus STA tools.
• Scripting in TCL, Python, Perl, Unix shell and flow automation.
• Experience with revision control, issue management and CI/CD tools.
• Excellent communication, multitasking, and problem-solving abilities.

Responsibilities

• Develop and deploy timing signoff methodologies for advanced technology nodes.
• Design and implement SOC, 3D/2.5D IC & multi-die signoff solutions.
• Participate & Lead in EDA flow development for Primetime, Tempus & Innovus.

Skills

Timing Signoff

SOC timing

3D/2.5D timing

Primetime

Tempus

Innovus

TCL scripting

Python scripting

Unix shell

Flow automation

Revision control

CI/CD tooling

Data analysis

Communication skills

Multitasking

Team collaboration

Education

BS in EE/CS 12+ years

MS/PhD in EE/CS 10+ years

Tools

Primetime

Tempus

Innovus

TCL

Python

Unix shell

Job description

Broadcom is seeking an experienced Timing Sign-Off engineer to join the Central Engineering Timing Sign-Off group. The role focuses on developing and deploying timing sign-off methodologies for advanced technology nodes and leading complex SOC/3D/2.5D IC timing initiatives.

You will collaborate across teams, own simulations, and mentor others while delivering high-yield solutions on time. Proficiency with STA tools (Primetime/Tempus) and scripting (TCL/Python) is required, with tapeout