Lead Radiation-Hardened Standard Cell Designer

JRC Integrated Systems; Saint Paul (MN); On-site; USD 120,000 - 190,000; Full time

Benefits offered by this job

Competitive compensation

Excellent benefits

DoD program exposure

Collaborative work environment

Professional growth opportunities

Job summary

JRC Integrated Systems seeks a Senior Standard Cell Design Engineer to lead Radiation Hardened LEAP library development and collaborate with foundries on MPW runs. You will shape simulation tools for reliability prediction and drive PPA optimization for extreme environments.

You have deep semiconductor design experience, hands-on standard cell and layout skills, and familiarity with Virtuoso/Spectre/HSPICE. Eligibility for a U.S. security clearance is required.

Qualifications

• Master’s degree or equivalent with 2+ years of industry experience.
• Bachelor’s degree with 4+ years of industry experience is also acceptable.
• Eligibility for U.S. security clearance due to defense-related projects.
• Deep knowledge of semiconductor design methodologies and principles.

Responsibilities

• Design and develop Radiation Hardened LEAP Standard Cell Libraries across multiple nodes.
• Create and validate new standard cells and IP including logic, sequential, and power cells.
• Use SPICE tools to estimate radiation-induced error rates for circuit resilience.
• Characterize libraries to optimize power, performance, and area in harsh environments.
• Collaborate with foundries on MPW runs and provide design support to customers.
• Contribute to proprietary simulation software and automation tooling for reliability prediction.

Skills

Semiconductor design

Standard cell design

Circuit design

SPICE tools

HSPICE

Power integrity

Reliability modeling

MPW testing

Design workflows

Python/TCL scripting

Education

Master’s degree

Bachelor’s degree

Tools

Virtuoso

Spectre

HSPICE (tool)

Liberate

PrimeLib

SiSmart

Job description

JRC Integrated Systems seeks a Senior Standard Cell Design Engineer to lead Radiation Hardened LEAP library development and collaborate with foundries on MPW runs. You will shape simulation tools for reliability prediction and drive PPA optimization for extreme environments.

You have deep semiconductor design experience, hands-on standard cell and layout skills, and familiarity with Virtuoso/Spectre/HSPICE. Eligibility for a U.S. security clearance is required.