Senior Radiation-Hardened Standard Cell Engineer

JRC Careers; Sunnyvale, Saint Paul (CA, MN); On-site; USD 140,000 - 200,000; Full time

Benefits offered by this job

Competitive compensation

Excellent benefits

DoD program impact

Collaborative environment

Professional growth

Job summary

JRC Careers in Sunnyvale, CA invites you to join our Semiconductor Technology Team as a Senior Standard Cell Design Engineer. You will lead the development of the LEAP Standard Cell Library, shape simulation tools for radiation reliability, and collaborate with foundry partners on MPW runs.

This role requires deep experience in standard cell and library design, SPICE-based characterization, and RHBD for SEE/SEU mitigation, with eligibility for a U.S. security clearance.

Qualifications

• Master’s degree with 2+ years or Bachelor’s with 4+ years.
• U.S. security clearance eligibility.
• Deep semiconductor design knowledge.
• Hands-on standard cell design and layout with Virtuoso, Spectre, HSPICE.
• Experience with test-chip designs and MPW execution.
• Proficiency in DRC/LVS, timing, and power integrity.
• Library characterization tool experience.
• Master’s with 5+ years or Bachelor with 7+ years in industry.
• GAA node design experience (e.g., Intel 18A) and memory design knowledge.
• Experience with Liberate, PrimeLib, SiSmart.
• RHBD for SEE/SEU; strong C++ and scripting (Python/TCL).

Responsibilities

• Execute design and development of Radiation Hardened LEAP standard cells across nodes.
• Generate and validate standard cells and IP including combinational and sequential logic.
• Leverage SPICE tools to calculate radiation-induced error rates for resilience.
• Execute library characterizations to optimize PPA in harsh environments.
• Collaborate with foundry partners on MPW runs and provide customer design support.
• Contribute to proprietary simulation software and automation scripts.

Skills

Radiation Hardened design

Standard cell design

Library development

SPICE tools

Test-chip MPW execution

Python scripting

C++

RHBD for SEE/SEU

Memory design

Education

Master’s degree with 2+ years experience

Bachelor’s degree with 4+ years experience

Tools

Virtuoso

Spectre

HSPICE

Liberate

PrimeLib

SiSmart

Job description

JRC Careers in Sunnyvale, CA invites you to join our Semiconductor Technology Team as a Senior Standard Cell Design Engineer. You will lead the development of the LEAP Standard Cell Library, shape simulation tools for radiation reliability, and collaborate with foundry partners on MPW runs.

This role requires deep experience in standard cell and library design, SPICE-based characterization, and RHBD for SEE/SEU mitigation, with eligibility for a U.S. security clearance.