Senior Standard Cell Design Engineer

JRC Careers; Sunnyvale, Saint Paul (CA, MN); On-site; USD 140,000 - 200,000; Full time

Benefits offered by this job

Competitive compensation

Excellent benefits

DoD program impact

Collaborative environment

Professional growth

Job summary

JRC Careers in Sunnyvale, CA invites you to join our Semiconductor Technology Team as a Senior Standard Cell Design Engineer. You will lead the development of the LEAP Standard Cell Library, shape simulation tools for radiation reliability, and collaborate with foundry partners on MPW runs.

This role requires deep experience in standard cell and library design, SPICE-based characterization, and RHBD for SEE/SEU mitigation, with eligibility for a U.S. security clearance.

Qualifications

• Master’s degree with 2+ years or Bachelor’s with 4+ years.
• U.S. security clearance eligibility.
• Deep semiconductor design knowledge.
• Hands-on standard cell design and layout with Virtuoso, Spectre, HSPICE.
• Experience with test-chip designs and MPW execution.
• Proficiency in DRC/LVS, timing, and power integrity.
• Library characterization tool experience.
• Master’s with 5+ years or Bachelor with 7+ years in industry.
• GAA node design experience (e.g., Intel 18A) and memory design knowledge.
• Experience with Liberate, PrimeLib, SiSmart.
• RHBD for SEE/SEU; strong C++ and scripting (Python/TCL).

Responsibilities

• Execute design and development of Radiation Hardened LEAP standard cells across nodes.
• Generate and validate standard cells and IP including combinational and sequential logic.
• Leverage SPICE tools to calculate radiation-induced error rates for resilience.
• Execute library characterizations to optimize PPA in harsh environments.
• Collaborate with foundry partners on MPW runs and provide customer design support.
• Contribute to proprietary simulation software and automation scripts.

Skills

Radiation Hardened design

Standard cell design

Library development

SPICE tools

Test-chip MPW execution

Python scripting

C++

RHBD for SEE/SEU

Memory design

Education

Master’s degree with 2+ years experience

Bachelor’s degree with 4+ years experience

Tools

Virtuoso

Spectre

HSPICE

Liberate

PrimeLib

SiSmart

Job description

At JRC, we tackle some of the toughest challenges faced by the Department of Defense (DoD) and other government agencies. Our expertise in engineering innovation and semiconductor technologies allows us to deliver mission-critical microelectronics solutions, aerospace systems engineering, and cutting‑edge research and development. By joining JRC, you’ll be part of a team that supports strategic deterrence and defense missions, playing a crucial role in ensuring the safety and security of the United States and its allies.

Join JRC's Semiconductor Technology Team!

Join JRC’s cutting‑edge Semiconductor Technology team as a Senior Standard Cell Design Engineer and lead the development of next‑generation radiation‑hardened microelectronics. In this high‑impact role, you’ll drive the technical execution of our LEAP Standard Cell Library, shape proprietary simulation tools for radiation‑induced reliability prediction, and collaborate closely with foundry partners on advanced-node designs.

You’ll architect and validate new standard cells across multiple technologies, optimize PPA under extreme conditions, support MPW test‑chip runs, and advance key automation and modeling capabilities. This role is ideal for an engineer who thrives at the intersection of device physics, circuit design, and reliability modeling.

We’re looking for someone with deep semiconductor design expertise, hands‑on experience in standard cell and library development, strong simulation and characterization skills, and eligibility for a U.S. security clearance. Experience with advanced nodes, RHBD techniques, memory design, and characterization tools is a strong plus.

If you’re excited about building resilient microelectronics that power mission‑critical systems, we’d love to meet you.

What You'll Do

• Execute the design and development of Radiation Hardened LEAP Standard Cell Libraries across multiple advanced foundry technology nodes.
• Generate and validate new standard cells and IP, including combinatorial logic, sequential logic, and power management cells.
• Leverage in-house software and industry-standard SPICE tools to calculate radiation-induced error rates to ensure circuit resilience.
• Execute advanced library characterizations to optimize Power, Performance, and Area (PPA) in harsh environments.
• Collaborate directly with external foundry partners on Multi-Product Wafer (MPW) runs and provide technical design support to customers.
• Contribute to the development of proprietary simulation software and automation scripts to improve reliability prediction.

What You Bring

• Master’s degree with 2+ years of direct industry experience, OR a Bachelor’s degree with 4+ years of experience.
• Must be eligible to obtain a U.S. security clearance due to the nature of defense‑related projects.
• Deep knowledge of semiconductor design methodologies and principles.
• Hands‑on experience with standard cell design, circuit design, and layout, and associated design tools (e.g. Virtuoso, Spectre, HSPICE)
• Demonstrated experience being involved in test‑chip designs and MPW execution.
• Proficiency in design flows including DRC/LVS, timing analysis, and power integrity.
• Extensive experience with simulation tools, specifically for library characterization.
• Master’s degree with 5+ years of experience, or Bachelor’s with 7+ years in industry.
• Hands‑on design experience with GAA nodes (e.g., Intel 18A), including device architecture and design‑rule familiarity.
• Proven background in SRAM/NVM bitcell design and/or memory compiler development.
• Practical experience with Liberate, PrimeLib, and SiSmart for characterization and modeling.
• Expertise in RHBD for SEE/SEU mitigation, plus proficiency in C++ and scripting (Python/TCL) across advanced nodes (FinFET, GAA, SOI).

At JRC we offer...

• A competitive compensation package
• An exceptional employee benefits program, providing support for our team members' well-being and success
• The chance to contribute to a high-profile Department of Defense programs and make a positive impact
• A collaborative work environment where teamwork, creativity, and innovation thrive
• Opportunities for professional growth and development, helping you advance your career

Voluntary Self-Identification

For government reporting purposes, we ask candidates to respond to the below self-identification survey.Completion of the form is entirely voluntary. Whatever your decision, it will not be considered in the hiringprocess or thereafter. Any information that you do provide will be recorded and maintained in aconfidential file.

As set forth in JRC Careers’s Equal Employment Opportunity policy,we do not discriminate on the basis of any protected group status under any applicable law.

If you believe you belong to any of the categories of protected veterans listed below, please indicate by making the appropriate selection.As a government contractor subject to the Vietnam Era Veterans Readjustment Assistance Act (VEVRAA), we request this information in order to measurethe effectiveness of the outreach and positive recruitment efforts we undertake pursuant to VEVRAA. Classification of protected categoriesis as follows:

A "disabled veteran" is one of the following: a veteran of the U.S. military, ground, naval or air service who is entitled to compensation (or who but for the receipt of military retired pay would be entitled to compensation) under laws administered by the Secretary of Veterans Affairs; or a person who was discharged or released from active duty because of a service‑connected disability.

A "recently separated veteran" means any veteran during the three‑year period beginning on the date of such veteran's discharge or release from active duty in the U.S. military, ground, naval, or air service.

An "active duty wartime or campaign badge veteran" means a veteran who served on active duty in the U.S. military, ground, naval or air service during a war, or in a campaign or expedition for which a campaign badge has been authorized under the laws administered by the Department of Defense.

An "Armed forces service medal veteran" means a veteran who, while serving on active duty in the U.S. military, ground, naval or air service, participated in a United States military operation for which an Armed Forces service medal was awarded pursuant to Executive Order 12985.