Design Verification Architect / Director

Cadence

Austin (TX)

On-site

USD 186,000 - 345,000

Full time

3 days ago
Be an early applicant
Application generator

Stand out for this role — generate a tailored resume and cover letter in about a minute.

Get past ATS filters

Job summary

Cadence is seeking a Design Verification Team Director to lead the Processor Verification group responsible for verifying microprocessor cores and peripherals. The role focuses on planning, building flexible testbenches, and driving coverage closure with cross-functional teams.

Ideal candidates have 17+ years of verification experience, a strong leadership track record, deep knowledge of SystemVerilog/UVM, and experience in automated verification flows.

Qualifications

  • 17+ years of design verification experience
  • BS (or higher) in EE/Computer Engineering
  • Proven experience at leading/managing team
  • Strong managerial, leadership and interpersonal skills
  • Excellent knowledge of computer architecture and design verification fundamentals
  • Thorough understanding of System Verilog, UVM, and other programming languages to build flexible and reusable complex testbenches
  • Exposure to scripting languages like Perl, Unix shell or similar languages
  • Experience with Assembly Language Programming Required
  • Experience with Formal Verification will be a plus
  • Experience with the development of fully automated flows
  • Experience with Gate Level Simulations
  • Excellent written and oral communication skills necessary
  • Knowledge of processor verification required

Responsibilities

  • Lead and run the Processor Verification team
  • Verify microprocessor cores and their peripherals
  • Craft verification plans and execute them
  • Implement simulation or emulation testbenches, assembly/C diagnostics, assertion checkers or coverage monitors
  • Manage coverage collection and closure
  • Coordinate with DV/Arch/Design/FW teams to identify coverage scope
  • Oversee 7-10 engineers team

Skills

Design verification experience
Leadership & management
SystemVerilog/UVM
Scripting languages (Perl, Unix shell)
Assemby language programming
Formal verification
Automated flows
Gate level simulations
Communications skills
Processor verification knowledge

Education

BS in EE/Computer Engineering

Job description

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Location

San Jose, CA and Austin, TX

Job Description

As a Design Verification Team Director, lead and run the Processor Verification team, you will be responsible for the verification of microprocessor cores and their peripherals

Responsibilities
  • Relevant experience in-order/out-of-order CPU cores and memory subsystem strongly preferred
  • Crafting verification plans and executing them to verify highly complex CPU designs.
  • You will implement simulation or emulation testbenches, assembly/C language diagnostics, assertion checkers or coverage monitors to meet target verification goals.
  • You will be responsible for coverage collection and closure
  • You will work closely with cross-functional teams (DV/Arch/Design/FW) to identify coverage scope
  • Tracking and reporting the work of 7-10 engineers
Required Skills And Experience
  • 17+ years of design verification experience
  • BS (or higher) in EE/Computer Engineering
  • Proven experience at leading/managing team.
  • Strong managerial, leadership and interpersonal skills
  • Excellent knowledge of computer architecture and design verification fundamentals
  • Thorough understanding of System Verilog, UVM, and other programming languages to build flexible and reusable complex testbenches
  • Exposure to scripting languages like Perl, Unix shell or similar languages
Experience With Assembly Language Programming Required
  • Experience with Formal Verification will be a plus
  • Experience with the development of fully automated flows
  • Experience with Gate Level Simulations
  • Excellent written and oral communication skills necessary
  • Knowledge of processor verification required

The annual salary range for California is $185,500 to $344,500. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.

We’re doing work that matters. Help us solve what others can’t.

Get your free, confidential resume review.

or drag and drop your file here.

Similar jobs

Similar jobs worth comparing

Design Verification Architect / Director
Design Verification Architect / Director

Cadence • San Jose (CA)

On-site
USD 186,000 - 345,000
Design Verification Architect / Director
Design Verification Architect / Director

Cadence Design Systems • San Jose (CA)

On-site
USD 186,000 - 345,000
Paid vacation
401(k) with match
Employee stock purchase plan
+2
Lead CPU Verification Architect — Equity Eligible
Lead CPU Verification Architect — Equity Eligible

Cadence Design Systems • San Jose (CA)

On-site
USD 186,000 - 345,000
Paid vacation
401(k) with match
Employee stock purchase plan
+2
CPU Verification Director – Core & Memory Architect
CPU Verification Director – Core & Memory Architect

Cadence Design Systems • San Jose (CA)

Hybrid
USD 186,000 - 345,000
Lead Processor Verification Architect
Lead Processor Verification Architect

Cadence • San Jose (CA)

On-site
USD 186,000 - 345,000
Sr. Principal Software Engineer, Physical Verification
Sr. Principal Software Engineer, Physical Verification

Cadence • San Jose (CA)

On-site
USD 161,000 - 299,000
Design Verification Engineer
Design Verification Engineer

Cerebras • Sunnyvale (CA)

On-site
USD 190,000 - 230,000
Principal Verification Engineer
Principal Verification Engineer

OSI Engineering • United States

Hybrid
USD 170,000 - 196,000
Director, Processor Verification & Testbenches
Director, Processor Verification & Testbenches

Cadence • Austin (TX)

On-site
USD 186,000 - 345,000
Software Architect, Physical Verification
Software Architect, Physical Verification

Cadence • San Jose (CA)

On-site
USD 178,000 - 332,000
Paid Vacation
401(k) plan with employer match
Employee Stock Purchase Plan
+1