Principal Validation Engineer

Astera Labs; San Francisco (CA); On-site; USD 180,000 - 240,000; Full time

Job summary

Astera Labs seeks a Post-Silicon Validation Engineer to develop and execute electrical validation tests for parametric performance, margins, and robustness of connectivity products. You will automate IC and board testing, design experiments, and report results to certify conformance with customer requirements.

Ideal candidates have 15+ years in SoC/silicon validation for server/storage/networking, strong Python skills, bench automation experience, and familiarity with high-speed PHY blocks and

Qualifications

• Bachelor’s degree in Electrical or Computer Engineering; Master’s preferred.
• ≥15 years of exp with SoC/Silicon for server/storage/networking.
• Experience with high-speed design blocks: PLLs, CDR/DFE, Tx EQ.
• Strong Python scripting and bench automation experience.

Responsibilities

• Develop and execute electrical validation tests to quantify performance and margins.
• Automate IC and board product testing; design experiments for root-cause analysis.
• Report results and ensure conformance to requirements; work with internal customers.

Skills

Python scripting

Bench automation

Data analysis

Git / DevOps

Education

Bachelor's degree in Electrical or Computer Engineering

Master's degree preferred

Tools

Cadence

Altium

MATLAB

Keysight ADS

PLTS

Job description

The mission of this role is to develop and execute electrical validation tests to quantify parametric device performance and margins over all system conditions. The validation team holds customers’ requirements in the highest regard and is solely responsible for certifying a product’s parametric conformance to this high bar. At Astera Labs, we are looking for motivated Post-Silicon Validation Engineers to work on our game-changing portfolio of connectivity products for Artificial Intelligence and Machine Learning applications. In this role you will formulate a comprehensive post-Silicon validation plan, automate the testing of ICs and board products, design experiments to root-cause unexpected behavior, report results and specification compliance, and work with key internal customers to quantify margins and ensure robustness.

• Strong academic and technical background in Electrical or Computer Engineering. At minimum, a Bachelor’s is required, and a Master’s is preferred.
• ≥15 years experience supporting or developing complex SoC/silicon products for Server, Storage, and/or Networking applications.
• Professional attitude with the ability to prioritize a dynamic list of multiple tasks, to plan and prepare for internal meetings in advance, and to work with minimal guidance and supervision.
• Entrepreneurial, open-minded behavior and can-do attitude. Think and act with the customer in mind!
• Proven track record solving problems independently, preferably as a tech lead

Required experience

• Familiarity with High-Speed SerDes PCIe5/6 Electrical Compliance specs, or 802.3 Ethernet
• Working knowledge of key, high-speed design blocks such as PLL’s, CDR DFE, Tx EQ
• Experience in system testing, characterization, margin analysis and optimization of high-speed PHY data links over long and short channels
• Strong python scripting ability: knowledge of object-oriented programming and basic dev ops using git for source control and collaboration
• Deep background in developing bench automation techniques, preferably using Python, with emphasis on execution efficiency, repeatability, and data analysis.
• Proficiency using high-speed lab equipment such as BERT, Oscilloscope, and VNA

Preferred experience

• Hands-on experience with signal integrity, especially as it relates to PCIe testing and CEM/NVMe interfaces
• Familiarity with IEEE 802.3x Ethernet standards and both NRZ and PAM-4 signaling
• Working knowledge of common serial data specifications such as I2C, SPI, etc
• Knowledge of schematic capture and PCB layout tools from Cadence, Altium, etc.
• Knowledge of simulation tools such as MATLAB, Keysight ADS, or PLTS for data analysis and modeling of electrical channel and signal integrity issues