Lead Post-Silicon DVT Engineer for High-Speed ASICs

Celero Communications, Inc.; Irvine (CA); On-site; USD 150,000 - 250,000; Full time

Job summary

Celero Communications, Inc. is seeking a Principal Design Validation & Test (DVT) Engineer in Irvine, CA to spearhead post-silicon validation for next-generation coherent DSP ASICs enabling AI and hyperscale networking.

You will drive silicon characterization, enable first silicon bring-up, and build validation infrastructure while collaborating across Architecture, RTL, Firmware, Systems, and Customer Engineering. Strong leadership and a strategic validation mindset are required.

Qualifications

• 8+ years in post-silicon validation, DVT, or silicon bring-up with complex ASICs/SoCs.
• Experience bringing first silicon to production in networking, data center, AI, or HPC products.
• Strong understanding of silicon debug methodologies and root-cause analysis.
• Proficient in Python for automation, regression, and data analysis.
• Experience validating firmware, embedded software, drivers, and HW/SW interfaces.

Responsibilities

• Lead post-silicon validation and characterization from first silicon through production release.
• Develop validation plans for functionality, performance, interoperability, stress, and reliability.
• Enable first silicon bring-up using JTAG, scan, and embedded debug features.
• Validate high-speed interfaces like PCIe, Ethernet, SerDes, CXL, SPI, I2C, MDIO.
• Develop automation frameworks for test execution, regression, and data analysis.
• Document validation results and production readiness reports.

Skills

Post-silicon validation

Python automation

Root-cause analysis

Hardware debugging

Cross-functional collaboration

Communication skills

On-site work readiness

Education

Bachelor's or Master's in Electrical/Computer Engineering

Tools

Oscilloscopes

BERTs

Protocol analyzers

Logic analyzers

Network analyzers

Power measurement equipment

Job description

Celero Communications, Inc. is seeking a Principal Design Validation & Test (DVT) Engineer in Irvine, CA to spearhead post-silicon validation for next-generation coherent DSP ASICs enabling AI and hyperscale networking.

You will drive silicon characterization, enable first silicon bring-up, and build validation infrastructure while collaborating across Architecture, RTL, Firmware, Systems, and Customer Engineering. Strong leadership and a strategic validation mindset are required.