Principal DVT Engineer – Post-Silicon for AI DSPs

Celero Communications, Inc.; Irvine (CA); Hybrid; USD 180,000 - 240,000; Full time

Job summary

Celero Communications, Inc. in Irvine, CA is seeking a Principal Design Validation & Test (DVT) Engineer to lead post-silicon validation for next-generation coherent DSP ASICs powering AI and hyperscale optical networking.

You will drive silicon characterization and readiness for customer deployment. You will collaborate across Architecture, RTL, Firmware, Systems and Customers, shaping validation strategy, building automation frameworks in Python, and ensuring production-ready validation

Qualifications

• 8+ years in post-silicon validation or silicon bring-up.
• Experience bringing first silicon to production in networking, data center, AI, or HPC products.
• Strong debugging and structured root-cause analysis.

Responsibilities

• Lead post-silicon validation and characterization from first silicon through production release.
• Develop validation plans covering functionality, performance, interoperability, compliance, stress testing, and reliability.
• Enable first silicon bring-up using JTAG, scan, embedded debug features, and board-level diagnostics.
• Validate high-speed interfaces including PCIe, Ethernet, SerDes, CXL, SPI, I2C, MDIO, and other protocols.
• Develop Python-based automation for test execution, regression, silicon characterization, data analysis, and reporting.
• Document validation results and production readiness reports.

Skills

Post-silicon validation

DVT engineering

Python automation

Lab equipment usage

Strong communication

Education

Bachelor's or Master's in Electrical Engineering

Tools

Oscilloscopes

BERTs

Protocol analyzers

Network analyzers

Logic analyzers

Power measurement equipment

Job description

Celero Communications, Inc. in Irvine, CA is seeking a Principal Design Validation & Test (DVT) Engineer to lead post-silicon validation for next-generation coherent DSP ASICs powering AI and hyperscale optical networking.

You will drive silicon characterization and readiness for customer deployment. You will collaborate across Architecture, RTL, Firmware, Systems and Customers, shaping validation strategy, building automation frameworks in Python, and ensuring production-ready validation