Senior DFT Engineer — ASIC/SoC Test & Signoff

Celero Communications, Inc.; Irvine (CA); Sur place; USD 230 000 - 275 000; Plein temps

Résumé du poste

Celero Communications is seeking a talented DFT Engineer to join our silicon engineering organization in Irvine, CA. You will partner with design, verification, physical design, product, and manufacturing teams to implement robust Design-for-Test methodologies for high-quality, high-volume production of complex ASIC and SoC products.

You will develop DFT architecture, perform scan insertion, ATPG, MBIST, and on-chip test features, while collaborating with RTL and hardware teams to ensure

Qualifications

• Bachelor’s degree in Electrical Engineering, Computer Engineering, or related field.
• 8+ years of ASIC/SoC DFT experience.
• Strong understanding of scan, ATPG, fault models, and test coverage methodologies.
• Experience with industry-standard DFT tools.
• Knowledge of Verilog/SystemVerilog and digital design fundamentals.
• Linux and scripting using Python, Tcl, Perl, or Shell.
• Results-driven engineer with strong debugging abilities.
• Comfortable working in fast-paced cross-functional environments.
• Passion for delivering high-quality silicon products.

Responsabilités

• Develop and implement DFT architecture for ASIC and SoC designs.
• Perform scan insertion, scan chain planning, and scan compression implementation.
• Generate and validate ATPG patterns and analyze fault coverage results.
• Implement and verify MBIST, and other on-chip test features.
• Collaborate with RTL, verification, and physical design teams to ensure successful DFT integration.
• Support JTAG and boundary-scan implementation and debug.
• Drive DFT signoff activities and manufacturing test readiness.
• Participate in silicon bring-up, failure analysis, and yield improvement efforts.

Connaissances

Verilog/SystemVerilog

Digital design fundamentals

Debugging

Cross-functional collaboration

Formation

Bachelor’s degree in Electrical Engineering, Computer Engineering, or related field

Outils

Synopsys TestMAX/TetraMAX

DFT Compiler

Siemens Tessent

Cadence Modus

Description du poste

Celero Communications is seeking a talented DFT Engineer to join our silicon engineering organization in Irvine, CA. You will partner with design, verification, physical design, product, and manufacturing teams to implement robust Design-for-Test methodologies for high-quality, high-volume production of complex ASIC and SoC products.

You will develop DFT architecture, perform scan insertion, ATPG, MBIST, and on-chip test features, while collaborating with RTL and hardware teams to ensure